Inventor

Brian R. Konigsburg

Inventor

Austin, TX, US

Overview

42→

Patents

1998–2020

Patent span

Physics

Primary field (CPC G)

Patents· 42 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing83%

G11CStatic stores9%

H01LSemiconductor devices2%

H03KPulse technique2%

H10NElectric solid-state devices not otherwise provided for2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

10,795,683Predicting indirect branches using problem branch filtering and pattern cache2020 10,685,002Radix sort acceleration using custom asic2020 10,545,739LLVM-based system C compiler for architecture synthesis2020 9,953,044Radix sort acceleration using custom ASIC2018 9,946,512Adaptive radix external in-place radix sort2018 9,928,261'Radix sort acceleration using custom ASIC'2018 9,858,373'In-cycle resource sharing for high-level synthesis of microprocessors'2018 9,779,803'Memory circuit with write-bypass portion'2017 9,741,419'Memory system with a content addressable superconducting memory'2017 9,715,411'Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system'2017 9,665,674'Automating a microarchitecture design exploration environment'2017 9,613,699'Memory system with a content addressable superconducting memory'2017 9,524,166'Tracking long GHV in high performance out-of-order superscalar processors'2016 9,507,891'Automating a microarchitecture design exploration environment'2016 9,495,170'Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall'2016 9,477,797'Automating a microarchitecture design exploration environment'2016 9,442,736'Techniques for selecting a predicted indirect branch address from global and local caches'2016 9,405,866'Automating a microarchitecture design exploration environment'2016 9,170,920'Identifying and tagging breakpoint instructions for facilitation of software debug'2015 9,081,895'Identifying and tagging breakpoint instructions for facilitation of software debug'2015 9,069,563'Reducing store-hit-loads in an out-of-order processor'2015 8,943,301'Storing branch information in an address table of a processor'2015 8,943,299'Operating a stack of information in an information handling system'2015 8,635,436'Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall'2014 7,984,280'Storing branch information in an address table of a processor'2011 7,487,334'Branch encoding before instruction cache write'2009 7,475,223'Fetch-side instruction dispatch group formation'2009 7,426,631'Methods and systems for storing branch information in an address table of a processor'2008 7,237,094'Instruction group formation and mechanism for SMT dispatch'2007 6,662,360'Method and system for software control of hardware branch prediction mechanism in a data processor'2003 6,622,236'Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions'2003 6,484,230'Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction'2002 6,412,051'System and method for controlling a memory array in an information handling system'2002 6,385,719'Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor'2002 6,304,959'Simplified method to generate BTAGs in a decode unit of a processing system'2001 6,286,094'Method and system for optimizing the fetching of dispatch groups in a superscalar processor'2001 6,279,105'Pipelined two-cycle branch target address cache'2001 6,021,467'Apparatus and method for processing multiple cache misses to a single cache line'2000 5,931,957'Support for out-of-order execution of loads and stores in a processor'1999 5,805,849'Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions'1998 5,802,571'Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory'1998 5,784,391'Distributed memory system with ECC and method of operation'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2020Patents assigned to IBM (37)· patent assignee history

1998–2020Based in Austin, TX, US· patent location history

2014–2015Patents assigned to KONIGSBURG BRIAN R (4)· patent assignee history

2015Patents assigned to LEVITAN DAVID S (2)· patent assignee history

2016Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history

2017Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (2)· patent assignee history

2017–2020Based in Glen Burnie, MD, US· patent location history

2017Based in Pasadena, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	37	1998–2020
KONIGSBURG BRIAN Rself	4	2014–2015
GLOBALFOUNDRIES INC	2	2016
LEVITAN DAVID S	2	2015
MICROSOFT TECHNOLOGY LICENSING LLC	2	2017

Locations

Location	Patents	Span
Austin, Texas, US	38	1998–2020
Glen Burnie, Maryland, US	3	2017–2020
Pasadena, California, US	1	2017