Inventor

Jody B. Joyner

Inventor

Austin, TX, US

Overview

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 70 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing90%

H04LTransmission of digital information, e.g. telegraphic communication3%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

H04JMultiplex communication1%

H04QSelecting1%

PatentTitleYear

10,884,943Speculative checkin of ERAT cache entries2021 10,776,281Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency2020 10,671,537Reducing translation latency within a memory management unit using external caching structures2020 10,649,902Reducing translation latency within a memory management unit using external caching structures2020 10,599,569Maintaining consistency between address translations in a data processing system2020 10,380,031Ensuring forward progress for nested translations in a memory management unit2019 10,318,435Ensuring forward progress for nested translations in a memory management unit2019 9,384,136'Modification of prefetch depth based on high latency event'2016 9,378,144'Modification of prefetch depth based on high latency event'2016 9,355,035'Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold'2016 9,336,145'Techniques for cache injection in a processor system based on a shared state'2016 9,268,703'Techniques for cache injection in a processor system from a remote node'2016 9,218,292'Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler'2015 9,213,647'Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler'2015 8,417,778'Collective acceleration unit tree flow control and retransmit'2013 8,302,109'Synchronization optimized queuing system'2012 8,077,602'Performing dynamic request routing based on broadcast queue depths'2011 7,921,316'Cluster-wide system clock in a multi-tiered full-graph interconnect architecture'2011 7,827,428'System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture'2010 7,779,148'Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips'2010 7,526,631'Data processing system with backplane and processor books configurable to support both technical and commercial workloads'2009 7,502,917'High speed memory cloning facility via a lockless multiprocessor mechanism'2009 7,308,536'System bus read data transfers with data ordering control bits'2007 7,308,558'Multiprocessor data processing system having scalable data interconnect and data routing mechanism'2007 7,069,394'Dynamic data routing mechanism for a high speed memory cloner'2006 7,007,128'Multiprocessor data processing system having a data routing mechanism regulated through control communication'2006 6,996,693'High speed memory cloning facility via a source/destination switching mechanism'2006 6,986,013'Imprecise cache line protection mechanism during a memory clone operation'2006 6,986,011'High speed memory cloner within a data processing system'2006 6,928,524'Data processing system with naked cache line write operations'2005 6,915,390'High speed memory cloning facility via a coherently done mechanism'2005 6,910,062'Method and apparatus for transmitting packets within a symmetric multiprocessor system'2005 6,898,677'Dynamic software accessibility to a microprocessor system with a high speed memory cloner'2005 6,892,283'High speed memory cloner with extended cache coherency protocols and responses'2005 6,874,063'System bus read data transfers with data ordering control bits'2005 6,865,695'Robust system bus recovery'2005 6,848,003'Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response'2005 6,748,493'Method and apparatus for managing memory operations in a data processing system using a store buffer'2004 6,671,712'Multi-node data processing system having a non-hierarchical interconnect architecture'2003 6,601,145'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls'2003 6,591,321'Multiprocessor system bus protocol with group addresses, responses, and priorities'2003 6,591,307'Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response'2003 6,553,442'Bus master for SMP execution of global operations utilizing a single token with implied release'2003 6,546,469'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers'2003 6,546,470'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation'2003 6,546,468'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update'2003 6,535,957'System bus read data transfers with bus utilization based data ordering'2003 6,532,519'Apparatus for associating cache memories with processors within a multiprocessor data processing system'2003 6,519,649'Multi-node data processing system and communication protocol having a partial combined response'2003 6,519,665'Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request'2003 6,516,368'Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release'2003 6,507,880'Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens'2003 6,502,171'Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data'2002 6,493,814'Reducing resource collisions associated with memory units in a multi-level hierarchy memory system'2002 6,480,915'Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release'2002 6,477,613'Cache index based system address bus'2002 6,460,100'Bus snooper for SMP execution of global operations utilizing a single token with implied release'2002 6,460,101'Token manager for execution of global operations utilizing multiple tokens'2002 6,442,629'Bus protocol and token manager for execution of global operations utilizing a single token with multiple operations with explicit release'2002 6,360,297'System bus read address operations with data ordering preference hint bits for vertical caches'2002 6,353,875'Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions'2002 6,349,360'System bus read address operations with data ordering preference hint bits'2002 6,349,367'Method and system for communication in which a castout operation is cancelled in response to snoop responses'2002 6,343,344'System bus directory snooping mechanism for read/castout (RCO) address transaction'2002 6,343,347'Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction'2002 6,338,124'Multiprocessor system bus with system controller explicitly updating snooper LRU information'2002 6,324,617'Method and system for communicating tags of data access target and castout victim in a single data transfer'2001 6,321,305'Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data'2001 6,279,086'Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position'2001 6,275,909'Multiprocessor system bus with system controller explicitly updating snooper cache state information'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to IBM (69)· patent assignee history

2001–2021Based in Austin, TX, US· patent location history

2011–2016Patents assigned to JOYNER JODY B (5)· patent assignee history

2011–2016Patents assigned to ARIMILLI RAVI K (3)· patent assignee history

2011–2013Patents assigned to DRERUP BERNARD C (3)· patent assignee history

2011–2013Patents assigned to ARIMILLI LAKSHMINARAYANA B (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	69	2001–2021
JOYNER JODY Bself	5	2011–2016
ARIMILLI RAVI K	3	2011–2016
DRERUP BERNARD C	3	2011–2013
ARIMILLI LAKSHMINARAYANA B	2	2011–2013

Locations

Location	Patents	Span
Austin, Texas, US	70	2001–2021