Inventor
John G. Pellerin
Inventor
Hopewell Junction, NY, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices52%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
B05DProcesses for applying fluent materials to surfaces, in general4%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
PatentTitleYear
8,753,943'Replacement metal gate transistors with reduced gate oxide leakage'20148,445,975'Replacement metal gate transistors with reduced gate oxide leakage'20138,053,849'Replacement metal gate transistors with reduced gate oxide leakage'20117,902,599'Integrated circuit having long and short channel metal gate devices and method of manufacture'20117,723,192'Integrated circuit long and short channel metal gate devices and method of manufacture'20107,544,572'Multi-operational mode transistor with multiple-channel device structure'20097,253,484'Low-power multiple-channel fully depleted quantum well CMOSFETs'20077,223,698'Method of forming a semiconductor arrangement with reduced field-to active step height'20077,091,106'Method of reducing STI divot formation during semiconductor device fabrication'20067,091,118'Replacement metal gate transistor with metal-rich silicon layer and method for making the same'20067,074,657'Low-power multiple-channel fully depleted quantum well CMOSFETs'20066,780,776'Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer'20046,764,917'SOI device with different silicon thicknesses'20046,713,357'Method to reduce parasitic capacitance of MOS transistors'20046,580,122'Transistor device having an enhanced width dimension and a method of making same'20036,406,964'Method of controlling junction recesses in a semiconductor device'20026,399,493'Method of silicide formation by silicon pretreatment'20026,317,642'Apparatus and methods for uniform scan dispensing of spin-on materials'20016,228,758'Method of making dual damascene conductive interconnections and integrated circuit device comprising same'20016,191,030'Anti-reflective coating layer for semiconductor device'20015,986,344'Anti-reflective coating layer for semiconductor device'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2014Patents assigned to ADVANCED MICRO DEVICES INC (20)· patent assignee history
1999–2004Based in Austin, TX, US· patent location history
2006Patents assigned to IBM (1)· patent assignee history
2006–2014Based in Hopewell Junction, NY, US· patent location history
2006Based in Hopewell Jct., NY, US· patent location history
2013Patents assigned to PAN JAMES (1)· patent assignee history
2013Patents assigned to PELLERIN JOHN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 20 | 1999–2014 |
| IBM | 1 | 2006 |
| PAN JAMES | 1 | 2013 |
| PELLERIN JOHNself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hopewell Junction, New York, US | 10 | 2006–2014 |
| Austin, Texas, US | 10 | 1999–2004 |
| Hopewell Jct., New York, US | 1 | 2006 |