Inventor

Robin Cheung

Inventor

Cupertino, CA, US

Overview

1986–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 102 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests14%

C25DProcesses for the electrolytic or electrophoretic production of coatings5%

H10BElectronic memory devices5%

H10DInorganic electric semiconductor devices5%

H10NElectric solid-state devices not otherwise provided for4%

C23CCoating metallic material3%

Y10TTechnical subjects covered by former us classification3%

H05KPrinted circuits2%

PatentTitleYear

10,615,198Isolation structures in film-based image sensors2020 9,880,733'Multi-touch remote control method'2018 8,569,160'Device fabrication'2013 8,361,560'Immersion platinum plating solution'2013 8,317,910'Immersion platinum plating solution'2012 8,314,024'Device fabrication'2012 8,268,667'Memory device using ion implant isolated conductive metal oxide'2012 8,237,142'Continuous plane of thin-film materials for a two-terminal cross-point memory'2012 8,003,511'Memory cell formation using ion implant isolated conductive metal oxide'2011 7,897,951'Continuous plane of thin-film materials for a two-terminal cross-point memory'2011 7,888,711'Continuous plane of thin-film materials for a two-terminal cross-point memory'2011 7,742,323'Continuous plane of thin-film materials for a two-terminal cross-point memory'2010 7,497,932'Electro-chemical deposition system'2009 7,393,795'Methods for post-etch deposition of a dielectric film'2008 7,313,456'Method and apparatus for capturing and using design intent in an integrated circuit fabrication process'2007 7,312,146'Semiconductor device interconnect fabricating techniques'2007 7,192,494'Method and apparatus for annealing copper films'2007 7,074,626'Method and apparatus for providing intra-tool monitoring and control'2006 6,929,774'Method and apparatus for heating and cooling substrates'2005 6,893,548'Method of conditioning electrochemical baths in plating technology'2005 6,842,659'Method and apparatus for providing intra-tool monitoring and control'2005 6,824,666'Electroless deposition method over sub-micron apertures'2004 6,818,066'Method and apparatus for treating a substrate'2004 6,797,620'Method and apparatus for improved electroplating fill of an aperture'2004 6,753,248'Post metal barrier/adhesion film'2004 6,740,221'Method of forming copper interconnects'2004 6,658,763'Method for heating and cooling substrates'2003 6,645,550'Method of treating a substrate'2003 6,635,157'Electro-chemical deposition system'2003 6,572,010'Integrated solder bump deposition apparatus and method'2003 6,492,722'Metallized interconnection structure'2002 6,477,787'Method and apparatus for heating and cooling substrates'2002 6,455,415'Method of encapsulated copper (Cu) interconnect formation'2002 6,436,267'Method for achieving copper fill of high aspect ratio interconnect features'2002 6,400,030'Self-aligning vias for semiconductors'2002 6,357,143'Method and apparatus for heating and cooling substrates'2002 6,323,135'Method of forming reliable capped copper interconnects/with high etch selectivity to capping layer'2001 6,319,616'Scaled interconnect anodization for high frequency applications'2001 6,276,072'Method and apparatus for heating and cooling substrates'2001 6,271,120'Method of enhanced silicide layer for advanced metal diffusion barrier layer application'2001 6,258,223'In-situ electroless copper seed layer enhancement in an electroplating system'2001 6,258,220'Electro-chemical deposition system'2001 6,259,160'Apparatus and method of encapsulated copper (Cu) Interconnect formation'2001 6,245,670'Method for filling a dual damascene opening having high aspect ratio to minimize electromigration failure'2001 6,239,494'Wire bonding CU interconnects'2001 6,225,210'High density capping layers with improved adhesion to copper interconnects'2001 6,200,913'Cure process for manufacture of low dielectric constant interlevel dielectric layers'2001 6,153,521'Metallized interconnection structure and method of making the same'2000 6,153,523'Method of forming high density capping layers for copper interconnects with improved adhesion'2000 6,136,163'Apparatus for electro-chemical deposition with thermal anneal chamber'2000 6,124,201'Method for manufacturing semiconductors with self-aligning vias'2000 6,117,763'Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water'2000 6,110,829'Ultra-low temperature Al fill for sub-0.25 .mu.m generation of ICs using an Al-Ge-Cu alloy'2000 6,096,648'Copper/low dielectric interconnect formation with reduced electromigration'2000 6,083,842'Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug'2000 6,056,864'Electropolishing copper film to enhance CMP throughput'2000 6,048,802'Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines'2000 6,033,982'Scaled interconnect anodization for high frequency applications'2000 5,990,557'Bias plasma deposition for selective low dielectric insulation'1999 5,972,192'Pulse electroplating copper or copper alloys'1999 5,970,370'Manufacturing capping layer for the fabrication of cobalt salicide structures'1999 5,968,333'Method of electroplating a copper or copper alloy interconnect'1999 5,965,934'Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS'1999 5,955,786'Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines'1999 5,861,677'Low RC interconnection'1999 5,843,836'Tunneling technology for reducing intra-conductive layer capacitance'1998 5,837,618'Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines'1998 5,814,560'Metallization sidewall passivation technology for deep sub-half micrometer IC applications'1998 5,789,315'Eliminating metal extrusions by controlling the liner deposition temperature'1998 5,785,236'Advanced copper interconnect system that is compatible with existing IC wire bonding technology'1998 5,776,834'Bias plasma deposition for selective low dielectric insulation'1998 5,770,519'Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device'1998 5,760,480'Low RC interconnection'1998 5,693,566'Layered low dielectric constant technology'1997 5,691,573'Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines'1997 5,688,717'Construction that prevents the undercut of interconnect lines in plasma metal etch systems'1997 5,679,608'Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC'1997 5,674,781'Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application'1997 5,675,186'Construction that prevents the undercut of interconnect lines in plasma metal etch systems'1997 5,670,828'Tunneling technology for reducing intra-conductive layer capacitance'1997 5,665,641'Method to prevent formation of defects during multilayer interconnect processing'1997 5,654,589'Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application'1997 5,646,448'Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device'1997 5,639,691'Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device'1997 5,635,423'Simplified dual damascene process for multi-level metallization and interconnection structure'1997 5,625,231'Low cost solution to high aspect ratio contact/via adhesion layer application for deep sub-half micrometer back-end-of line technology'1997 5,559,055'Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance'1996 5,550,405'Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS'1996 5,539,247'Selective metal via plug growth technology for deep sub-micrometer ULSI'1996 5,534,731'Layered low dielectric constant technology'1996 5,471,093'Pseudo-low dielectric constant technology'1995 5,453,402'Selective metal via plug growth technology for deep sub-micrometer ULSI'1995 5,451,545'Process for forming stable local interconnect/active area silicide structure VLSI applications'1995 5,365,111'Stable local interconnect/active area silicide structure for VLSI applications'1994 4,892,844'Making a low resistance three layered contact for silicon devices'1990 4,871,962'Method for measuring the size of vias'1989 4,796,081'Low resistance metal contact for silicon devices'1989 4,762,805'Nitride-less process for VLSI circuit device isolation'1988 4,744,056'Stable high density RAM'1988 4,727,045'Plugged poly silicon resistor load for static random access memory cells'1988 4,693,925'Integrated circuit structure having intermediate metal silicide layer'1987 4,581,815'Integrated circuit structure having intermediate metal silicide layer and method of making same'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–2002Patents assigned to ADVANCED MICRO DEVICES INC (63)· patent assignee history

1986–2020Based in Cupertino, CA, US· patent location history

2000–2009Patents assigned to APPLIED MATERIALS INC (25)· patent assignee history

2010–2013Patents assigned to UNITY SEMICONDUCTOR CORP (10)· patent assignee history

2012–2018Patents assigned to CHEUNG ROBIN (7)· patent assignee history

2012–2013Patents assigned to RINERSON DARRELL (4)· patent assignee history

2018Based in San Diego, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	63	1986–2002
APPLIED MATERIALS INC	25	2000–2009
UNITY SEMICONDUCTOR CORP	10	2010–2013
CHEUNG ROBINself	7	2012–2018
RINERSON DARRELL	4	2012–2013

Locations

Location	Patents	Span
Cupertino, California, US	101	1986–2020
San Diego, California, US	1	2018