Inventor

Lew G. Chua-Eoan

Inventor
Carlsbad, CA, US

Overview

46→
Patents
1996–2017
Patent span
Physics
Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing24%
H03KPulse technique12%
G11CStatic stores10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
H01LSemiconductor devices6%
G01RMeasuring electric variables5%
H10DInorganic electric semiconductor devices5%
G05FSystems for regulating electric or magnetic variables3%
H05KPrinted circuits3%
PatentTitleYear
9,768,161'FinFET capacitor circuit'20179,613,675'System and method to perform low power memory operations'20179,508,607'Thermal management of tightly integrated semiconductor device, system and/or package'20169,430,407'Method and system for secure storage and retrieval of machine state'20169,411,745'Multi-core heterogeneous system translation lookaside buffer coherency'20169,349,692'Integrated voltage regulator with embedded passive device(s) for a stacked IC'20169,343,127'Memory device having an adaptable number of open rows'20169,281,036'Memory device having an adaptable number of open rows'20169,142,548'FinFET compatible capacitor circuit'20159,048,112'Integrated voltage regulator with embedded passive device(s) for a stacked IC'20159,001,267'Method and apparatus for tightly coupled, low power image processing'20158,924,902'Methods and circuits for optimizing performance and power consumption in a design and circuit employing lower threshold voltage (LVT) devices'20148,872,492'On-chip low voltage capacitor-less low dropout regulator with Q-control'20148,760,217'Semiconductor device having on-chip voltage regulator'20148,719,610'Low power electronic system architecture using non-volatile magnetic memory'20148,692,368'Integrated voltage regulator method with embedded passive device(s)'20148,527,797'System and method of leakage control in an asynchronous system'20138,508,301'Three dimensional inductor, transformer and radio frequency amplifier'20138,497,694'On-chip sensor for measuring dynamic power supply noise of the semiconductor chip'20138,451,048'Low voltage temperature sensor and use thereof for autonomous multiprobe measurement device'20138,354,875'Low voltage temperature sensor and use thereof for autonomous multiprobe measurement device'20138,295,082'Gate level reconfigurable magnetic logic'20128,258,812'Software programmable logic using spin transfer torque magnetoresistive devices'20128,193,630'System and method of silicon switched power delivery using a package'20128,143,952'Three dimensional inductor and transformer'20128,081,037'Ring oscillator using analog parallelism'20118,063,664'Distributed supply current switch circuits for enabling individual power domains'20118,040,154'Software programmable logic using spin transfer torque magnetoresistive devices'20117,961,502'Non-volatile state retention latch'20117,936,205'Leakage reduction in electronic circuits'20117,812,582'System and method of power distribution control of an integrated circuit'20107,728,622'Software programmable logic using spin transfer torque magnetoresistive random access memory'20107,659,746'Distributed supply current switch circuits for enabling individual power domains'20107,543,207'Full scan solution for latched-based design'20097,417,482'Adaptive voltage scaling for an electronics device'20087,246,287'Full scan solution for latched-based design'20077,242,237'Supply switch circuit for implementing a switchable on-chip high voltage supply'20077,181,639'Method and apparatus for controlling the flow of data between two circuits by generating one or more phase shifted clock signals'20077,003,686'Interface circuit'20066,883,156'Apparatus and method for relative position annotation of standard cell components to facilitate datapath design'20056,633,971'Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline'20036,574,651'Method and apparatus for arithmetic operation on vectored data'20036,351,803'Mechanism for power efficient processing in a pipeline processor'20025,682,495'Fully associative address translation buffer having separate segment and page invalidation'19975,530,822'Address translator and method of operation'19965,508,644'Sense amplifier for differential voltage detection with low input capacitance'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–1997Based in Austin, TX, US· patent location history
2002–2006Patents assigned to HITACHI LTD (4)· patent assignee history
2002–2009Based in San Jose, CA, US· patent location history
2007–2015Based in San Diego, CA, US· patent location history
2008–2017Patents assigned to QUALCOMM INC (33)· patent assignee history
2008–2017Based in Carlsbad, CA, US· patent location history
2011–2015Patents assigned to CHUA-EOAN LEW G (15)· patent assignee history
2011–2013Patents assigned to NOWAK MATTHEW (5)· patent assignee history
2011–2014Patents assigned to CHUA-EOAN LEW (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
QUALCOMM INC332008–2017
CHUA-EOAN LEW Gself152011–2015
NOWAK MATTHEW52011–2013
CHUA-EOAN LEWself42011–2014
HITACHI LTD42002–2006
Locations
LocationPatentsSpan
Carlsbad, California, US272008–2017
San Diego, California, US82007–2015
San Jose, California, US82002–2009
Austin, Texas, US31996–1997