Inventor
Ki-Hyun Hwang
Inventor
Seongnam-si, KR
Overview
Patents· 81 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H10BElectronic memory devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H01LSemiconductor devices12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
C23CCoating metallic material4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B82YSpecific uses or applications of nanostructures1%
G11CStatic stores1%
H10NElectric solid-state devices not otherwise provided for0%
PatentTitleYear
9,853,044Semiconductor device and method of fabricating the same20179,698,233'Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same'20179,613,800'Methods of manufacturing semiconductor devices including an oxide layer'20179,564,499'Three-dimensional semiconductor memory devices and methods of fabricating the same'20179,536,896'Non-volatile memory device having a vertical structure and method of fabricating the same'20179,530,899'Semiconductor memory device and method of manufacturing the same'20169,461,061'Vertical memory devices and methods of manufacturing the same'20169,431,416'Vertical-type nonvolatile memory device and method of manufacturing the same'20169,431,414'Vertical memory devices and methods of manufacturing the same'20169,368,646'Memory devices and methods of manufacturing the same'20169,368,508'Memory device'20169,343,546'Semiconductor device and method of manufacturing the same'20169,324,730'Vertical memory devices and methods of manufacturing the same'20169,276,133'Vertical memory devices and method of manufacturing the same'20169,257,573'Semiconductor device and method of fabricating the same'20169,240,357'Method of fabricating semiconductor device having preliminary stacked structure with offset oxide etched using gas cluster ion'20169,129,857'Semiconductor device including a first core pattern under a second core pattern'20159,111,897'Methods of forming a polysilicon layer and methods of manufacturing semiconductor devices'20159,082,659'Methods of forming vertical type semiconductor devices including oxidation target layers'20159,064,895'Vertical memory devices and methods of manufacturing the same'20159,064,736'Method of manufacturing three dimensional semiconductor memory device'20159,012,974'Vertical memory devices and methods of manufacturing the same'20158,994,091'Non-volatile memory device having a vertical structure and method of fabricating the same'20158,987,805'Vertical type semiconductor devices including oxidation target layers'20158,927,366'Method of manufacturing a non-volatile memory device having a vertical structure'20158,923,057'Three-dimensional semiconductor memory device with active patterns and electrodes arranged above a substrate'20148,901,643'Semiconductor device and method of manufacturing the same'20148,822,287'Methods of manufacturing semiconductor devices'20148,748,249'Vertical structure non-volatile memory device and method of manufacturing the same'20148,735,247'Method for fabricating nonvolatile memory device'20148,659,069'Gate structures'20148,637,917'Semiconductor devices including vertical channel pattern'20148,617,947'Method of manufacturing semiconductor device'20138,614,476'Nonvolatile memory devices and fabricating methods thereof'20138,592,269'Method of manufacturing gate structure and method of manufacturing semiconductor device including the same'20138,563,421'Method of fabricating semiconductor device'20138,525,275'Methods of forming non-volatile memory devices'20138,497,142'Methods of forming conductive layer patterns using gas phase cleaning process and methods of manufacturing semiconductor devices'20138,497,555'Vertical memory devices including indium and/or gallium channel doping'20138,460,999'Non-volatile memory devices with multiple layers having band gap relationships among the layers'20138,445,367'Methods of manufacturing semiconductor devices'20138,440,527'Memory device and method of fabricating the same'20138,435,877'Methods of manufacturing semiconductor devices'20138,426,304'Methods of manufacturing a vertical type semiconductor device'20138,410,542'Charge-trapping nonvolatile memory devices having gate structures therein with improved blocking layers'20138,330,207'Flash memory device including multilayer tunnel insulator and method of fabricating the same'20128,294,198'Semiconductor integrated circuit device and method of fabricating the same'20128,227,357'Methods of fabricating silicon oxide layers using inorganic silicon precursors and methods of fabricating semiconductor devices including the same'20128,129,264'Method of fabricating a semiconductor device'20128,114,735'Method of manufacturing a non-volatile memory device'20128,008,154'Methods of forming impurity containing insulating films and flash memory devices including the same'20117,973,355'Nonvolatile memory devices with multiple layers having band gap relationships among the layers'20117,951,671'Method of fabricating non-volatile memory device having separate charge trap patterns'20117,846,836'Method of forming a conductive structure in a semiconductor device and method of manufacturing a semiconductor device'20107,799,639'Methods of fabricating non-volatile memory devices including a chlorine cured tunnel oxide layer'20107,791,130'Non-volatile memory device and methods of forming the same'20107,723,755'Semiconductor having buried word line cell structure and method of fabricating the same'20107,622,383'Methods of forming conductive polysilicon thin films via atomic layer deposition and methods of manufacturing semiconductor devices including such polysilicon thin films'20097,510,935'Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device'20097,473,959'Non-volatile semiconductor memory devices and methods of fabricating the same'20097,419,888'Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same'20087,361,547'Method for forming a capacitor for use in a semiconductor device'20087,238,585'Method of forming a storage electrode of a semiconductor device'20077,153,750'Methods of forming capacitors of semiconductor devices including silicon-germanium and metallic electrodes'20067,119,029'Method of oxidizing a silicon substrate and method of forming an oxide layer using the same'20067,119,392'Storage electrode of a semiconductor device and method of forming the same'20067,007,933'Method and apparatus for supplying a source gas'20067,005,389'Methods for forming a thin film on an integrated circuit device by sequentially providing energies to activate the reactants'20066,911,364'One-cylinder stack capacitor and method for fabricating the same'20056,838,719'Dram cell capacitors having U-shaped electrodes with rough inner and outer surfaces'20056,809,363'Storage electrode of a semiconductor memory device'20046,797,561'Method of fabricating a capacitor of a semiconductor device'20046,730,570'Method for forming a self-aligned contact of a semiconductor device and method for manufacturing a semiconductor device using the same'20046,700,153'One-cylinder stack capacitor and method for fabricating the same'20046,620,686'Methods of forming capacitors having a polymer on a portion thereof that inhibits the formation of hemispherical grain (HSG) nodules on that portion and capacitors formed thereby'20036,583,056'Storage electrode of a semiconductor memory device and method for fabricating the same'20036,385,020'Methods of forming HSG capacitors from nonuniformly doped amorphous silicon layers and HSG capacitors formed thereby'20026,329,266'Methods of forming isolation trenches including damaging a trench isolation mask'20016,214,688'Methods of forming integrated circuit capacitors having U-shaped electrodes'20016,207,488'Method for forming a tantalum oxide capacitor using two-step rapid thermal nitridation'20016,162,700'Method of forming a trench isolation structure in a semiconductor substrate'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2017Patents assigned to SAMSUNG ELECTRONICS CO LTD (81)· patent assignee history
2000–2005Based in Kyungki-do, KR· patent location history
2001–2005Based in Yongin, KR· patent location history
2003–2016Based in Gyeonggi-do, KR· patent location history
2004–2008Based in Yongin-si, KR· patent location history
2010–2017Based in Seongnam-si, KR· patent location history
2012–2017Patents assigned to HWANG KI-HYUN (39)· patent assignee history
2012–2017Patents assigned to AHN JAE-YOUNG (16)· patent assignee history
2012–2016Patents assigned to CHOI HAN-MEI (13)· patent assignee history
2012–2016Patents assigned to YOO DONG-CHUL (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 81 | 2000–2017 |
| HWANG KI-HYUNself | 39 | 2012–2017 |
| AHN JAE-YOUNG | 16 | 2012–2017 |
| CHOI HAN-MEI | 13 | 2012–2016 |
| YOO DONG-CHUL | 12 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seongnam-si, KR | 51 | 2010–2017 |
| Gyeonggi-do, KR | 13 | 2003–2016 |
| Yongin-si, KR | 6 | 2004–2008 |
| Kyungki-do, KR | 6 | 2000–2005 |
| Yongin, KR | 3 | 2001–2005 |