Inventor
Mohamad A. Shaheen
Inventor
Portland, OR, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1038%
H10DInorganic electric semiconductor devices26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
B23KSoldering or unsoldering4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
H10BElectronic memory devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
8,735,946'Substrate having a charged zone in an insulating buried layer'20148,617,945'Stacking fault and twin blocking barrier for integrating III-V on Si'20138,535,996'Substrate having a charged zone in an insulating buried layer'20138,143,646'Stacking fault and twin blocking barrier for integrating III-V on Si'20128,084,818'High mobility tri-gate devices and methods of fabrication'20118,034,675'Semiconductor buffer architecture for III-V devices on silicon substrates'20117,851,780'Semiconductor buffer architecture for III-V devices on silicon substrates'20107,851,781'Buffer layers for device isolation of devices grown on silicon'20107,723,749'Strained semiconductor structures'20107,670,928'Ultra-thin oxide bonding for S1 to S1 dual orientation bonding'20107,573,059'Dislocation-free InSb quantum well structure on Si using novel buffer architecture'20097,569,857'Dual crystal orientation circuit devices on the same substrate'20097,494,911'Buffer layers for device isolation of devices grown on silicon'20097,473,614'Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer'20097,378,331'Methods of vertically stacking wafers using porous silicon'20087,355,247'Silicon on diamond-like carbon devices'20087,279,369'Germanium on insulator fabrication via epitaxial germanium bonding'20077,202,503'III-V and II-VI compounds as template materials for growing germanium containing film on silicon'20077,161,224'Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process'20077,157,379'Strained semiconductor structures'20077,148,122'Bonding of substrates'20067,052,978'Arrangements incorporating laser-induced cleaving'20067,042,009'High mobility tri-gate devices and methods of fabrication'20066,911,380'Method of forming silicon on insulator wafers'20056,908,027'Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process'20056,833,195'Low temperature germanium transfer'20046,645,831'Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2013Patents assigned to INTEL CORP (25)· patent assignee history
2003–2014Based in Portland, OR, US· patent location history
2011–2013Patents assigned to SHAHEEN MOHAMAD A (3)· patent assignee history
2012–2013Patents assigned to CHOW LOREN A (2)· patent assignee history
2012–2013Patents assigned to FASTENAU JOEL M (2)· patent assignee history
2012–2013Patents assigned to HUDAIT MANTU K (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 25 | 2003–2013 |
| SHAHEEN MOHAMAD Aself | 3 | 2011–2013 |
| CHOW LOREN A | 2 | 2012–2013 |
| FASTENAU JOEL M | 2 | 2012–2013 |
| HUDAIT MANTU K | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 27 | 2003–2014 |