Inventor
Marc R. Faucher
Inventor
South Burlington, VT, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing33%
G11CStatic stores10%
G01QScanning-probe techniques or apparatus8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H04LTransmission of digital information, e.g. telegraphic communication6%
B82YSpecific uses or applications of nanostructures4%
G01PMeasuring linear or angular speed, acceleration, deceleration, or shock4%
G01RMeasuring electric variables4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
B81BMicrostructural devices or systems, e.g. micromechanical devices2%
PatentTitleYear
11,099,205Prestrained vibrating accelerometer202110,527,645Compact probe for atomic-force microscopy and atomic-force microscope including such a probe202010,340,371Modulation device comprising a nanodiode201910,302,673Miniaturized and compact probe for atomic force microscopy20199,815,686'Microelectromechanical device and system with low-impedance resistive transducer'20178,481,163'Carbon nanotube growth method'20138,244,880'Connection management method, system, and program product'20128,146,046'Structures for semiconductor structures with error detection and correction'20128,091,143'Atomic force microscopy probe'20128,019,970'Three-dimensional networking design structure'20117,962,695'Method and system for integrating SRAM and DRAM architecture in set associative cache'20117,882,302'Method and system for implementing prioritized refresh of DRAM based cache'20117,865,694'Three-dimensional networking structure'20117,526,698'Error detection and correction in semiconductor structures'20096,578,155'Data processing system with adjustable clocks for partitioned synchronous interfaces'20036,532,520'Method and apparatus for allocating data and instructions within a shared cache'20036,457,155'Method for making a memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket'20026,185,718'Memory card design with parity and ECC for non-parity and non-ECC systems'20016,178,467'Microprocessor system requests burstable access to noncacheable memory areas and transfers noncacheable address on a bus at burst mode'20016,108,730'Memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket'20006,092,146'Dynamically configurable memory adapter using electronic presence detects'20006,052,818'Method and apparatus for ECC bus protection in a computer system with non-parity memory'20005,969,997'Narrow data width DRAM with low latency page-hit operations'19995,963,464'Stackable memory card'19995,959,845'Universal chip carrier connector'19995,548,746'Non-contiguous mapping of I/O addresses to use page protection of a process'19965,459,842'System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory'19955,448,521'Connecting a short word length non-volatile memory to a long word length address/data multiplexed bus'19955,404,543'Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2012Patents assigned to IBM (22)· patent assignee history
1995–2012Based in South Burlington, VT, US· patent location history
1999–2002Based in Burlington, VT, US· patent location history
2012–2021Patents assigned to CENTRE NAT RECH SCIENT (7)· patent assignee history
2012–2013Patents assigned to FAUCHER MARC (2)· patent assignee history
2012Patents assigned to AIME JEAN-PIERRE (1)· patent assignee history
2012Based in Lille, FR· patent location history
2013Based in Saint Egreve, FR· patent location history
2017–2020Patents assigned to VMICRO (3)· patent assignee history
2017–2021Based in Lesquin, FR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 22 | 1995–2012 |
| CENTRE NAT RECH SCIENT | 7 | 2012–2021 |
| VMICRO | 3 | 2017–2020 |
| FAUCHER MARCself | 2 | 2012–2013 |
| AIME JEAN-PIERRE | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 18 | 1995–2012 |
| Lesquin, FR | 5 | 2017–2021 |
| Burlington, VT, US | 4 | 1999–2002 |
| Saint Egreve, FR | 1 | 2013 |
| Lille, FR | 1 | 2012 |