Inventor
Aarti Gupta
Inventor
Princeton, NJ, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing77%
G01RMeasuring electric variables7%
G06NComputing arrangements based on specific computational models5%
H04LTransmission of digital information, e.g. telegraphic communication4%
B60RVehicles, vehicle fittings, or vehicle parts, not otherwise provided for2%
G10LSpeech analysis techniques or speech synthesis2%
G11CStatic stores2%
H04WWireless communication networks2%
PatentTitleYear
11,056,111Dynamic contact ingestion202110,382,532Cross-cloud object mapping for hybrid clouds20199,723,065'Cross-cloud object mapping for hybrid clouds'20178,799,194'Probabilistic model checking of systems with ranged probabilities'20148,719,802'Interprocedural exception method'20148,719,793'Scope bounding with automated specification inference for scalable software model checking'20148,707,278'Embedding class hierarchy into object models for multiple class inheritance'20148,601,459'Control structure refinement of loops using static analysis'20138,539,451'Systems and methods for model checking the precision of programs employing floating-point operations'20138,538,900'Integrating interval constraint propagation with nonlinear real arithmetic'20138,527,976'System and method for generating error traces for concurrency bugs'20138,522,226'Control structure refinement of loops using static analysis'20138,402,440'Program verification through symbolic enumeration of control path programs'20138,381,226'System and method for monotonic partial order reduction'20138,374,840'System and method for feedback-guided test generation for cyber-physical systems using monte-carlo'20138,365,152'Path-sensitive analysis through infeasible-path detection and syntactic language refinement'20138,359,578'Symbolic reduction of dynamic executions of concurrent programs'20138,286,137'Accelerating model checking via synchrony'20128,266,600'Model checking of multi threaded software'20128,200,474'Dynamic model checking with property driven pruning to detect race conditions'20128,191,045'Mining library specifications using inductive learning'20128,185,875'Fast and accurate static data-race detection for concurrent programs'20128,176,496'Partial order reduction using guarded independence relations'20128,136,098'Using pushdown systems for the static analysis of multi-threaded programs'20128,131,532'Software verification using range analysis'20128,126,831'System and method for dynamically inferring data preconditions over predicates by tree learning'20128,005,661'Modeling and verification of concurrent systems using SMT-based BMC'20118,006,239'Program analysis using symbolic ranges'20117,930,659'Software verification'20117,926,039'Reachability analysis for program verification'20117,853,906'Accelerating high-level bounded model checking'20107,784,035'Method for the static analysis of concurrent multi-threaded software'20107,743,352'Computer implemented method of high-level synthesis for the efficient verification of computer software'20107,742,907'Iterative abstraction using SAT-based BMC with proof analysis'20107,711,525'Efficient approaches for bounded model checking'20107,693,690'Disjunctive image computation for sequential systems'20107,386,818'Efficient modeling of embedded memories in bounded memory checking'20087,346,486'System and method for modeling, abstraction, and analysis of software'20087,305,637'Efficient SAT-based unbounded symbolic model checking'20077,203,917'Efficient distributed SAT and SAT-based distributed bounded model checking'20076,975,976'Property specific testbench generation framework for circuit design validation by guided simulation'20056,874,135'Method for design validation using retiming'20056,745,160'Verification of scheduling in the presence of loops using uninterpreted symbolic simulation'20046,728,665'SAT-based image computation with application in reachability analysis'20046,662,323'Fast error diagnosis for combinational verification'20036,651,234'Partition-based decision heuristics for SAT and image computation using SAT and BDDs'20036,496,961'Dynamic detection and removal of inactive clauses in SAT with application in image computation'20026,035,109'Method for using complete-1-distinguishability for FSM equivalence checking'20006,026,222'System for combinational equivalence checking'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2014Based in Princeton, NJ, US· patent location history
2003–2014Patents assigned to NEC CORP (9)· patent assignee history
2007–2014Patents assigned to NEC LAB AMERICA INC (36)· patent assignee history
2012–2014Patents assigned to GUPTA AARTI (21)· patent assignee history
2012–2014Patents assigned to IVANCIC FRANJO (11)· patent assignee history
2012–2014Patents assigned to SANKARANARAYANAN SRIRAM (9)· patent assignee history
2017–2019Based in San Jose, CA, US· patent location history
2021Based in Los Altos, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC LAB AMERICA INC | 36 | 2007–2014 |
| GUPTA AARTIself | 21 | 2012–2014 |
| IVANCIC FRANJO | 11 | 2012–2014 |
| NEC CORP | 9 | 2003–2014 |
| SANKARANARAYANAN SRIRAM | 9 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Princeton, New Jersey, US | 46 | 2000–2014 |
| San Jose, California, US | 2 | 2017–2019 |
| Los Altos, California, US | 1 | 2021 |