Inventor
Yung-I Yeh
Inventor
Kaohsiung, TW
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1049%
H01LSemiconductor devices13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H05KPrinted circuits10%
G06FElectric digital data processing5%
Y10TTechnical subjects covered by former us classification5%
G01BMeasuring length, thickness or similar linear dimensions3%
H01QAntennas, i.e. radio aerials3%
PatentTitleYear
10,797,022Semiconductor device package and method of manufacturing the same202010,593,630Semiconductor package and method for manufacturing the same20209,984,983Semiconductor packages with thermal-enhanced conformal shielding and related methods20189,960,137Semiconductor device package and method for forming the same20189,484,313'Semiconductor packages with thermal-enhanced conformal shielding and related methods'20168,786,060'Semiconductor package integrated with conformal shield and antenna'20147,375,020'Method of forming bumps'20087,061,084'Lead-bond type chip package and manufacturing method thereof'20066,960,822'Solder mask and structure of a substrate'20056,916,732'Method of forming bumps'20056,795,746'System for providing IC bonding diagram via network'20046,751,781'Thermal data automatic service system'20046,642,612'Lead-bond type chip package and manufacturing method thereof'20036,551,855'Substrate strip and manufacturing method thereof'20036,528,882'Thermal enhanced ball grid array package'20036,489,682'Ball grid array semiconductor package and substrate therefor'20026,423,622'Lead-bond type chip package and manufacturing method thereof'20026,313,413'Wire structure of substrate for layout detection'20016,291,898'Ball grid array package'20016,252,309'Packaged semiconductor substrate'20015,982,625'Semiconductor packaging device'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2020Patents assigned to ADVANCED SEMICONDUCTOR ENG (21)· patent assignee history
1999–2020Based in Kaohsiung, TW· patent location history
2014Patents assigned to CHUNG CHI-SHENG (1)· patent assignee history
2014Patents assigned to LIAO KUO-HSIEN (1)· patent assignee history
2014Patents assigned to YEH YUNG-I (1)· patent assignee history
2014Patents assigned to YEN HAN-CHEE (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED SEMICONDUCTOR ENG | 21 | 1999–2020 |
| CHUNG CHI-SHENG | 1 | 2014 |
| LIAO KUO-HSIEN | 1 | 2014 |
| YEH YUNG-Iself | 1 | 2014 |
| YEN HAN-CHEE | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 21 | 1999–2020 |