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Inventor

Jaesung Sim

Inventor
Hwaseong-si, KR

Overview

16→
Patents
2010–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 16 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores31%
H10BElectronic memory devices20%
H01LSemiconductor devices18%
H10DInorganic electric semiconductor devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
A61FFilters implantable into blood vessels2%
A61HPhysical therapy apparatus, e.g. devices for locating or stimulating reflex points in the body2%
G06FElectric digital data processing2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H05BElectric heating2%
PatentTitleYear
10,332,902Three-dimensional semiconductor memory device including vertically stacked electrodes201910,032,787Three-dimensional semiconductor memory device20189,952,775Unusable column mapping in flash memory devices20189,865,685'Three-dimensional semiconductor memory devices including a vertical channel'20189,847,341Three-dimensional semiconductor memory device20179,837,429Method of fabricating a three-dimensional semiconductor memory device having a plurality of memory blocks on a peripheral logic structure20179,595,333'Nonvolatile memory device and programming method thereof'20179,559,115'Three-dimensional semiconductor memory devices including a vertical channel'20179,515,087'Three-dimensional semiconductor memory device'20169,042,175'Non-volatile memory device and read method thereof'20158,953,382'Vertical nonvolatile memory devices and methods of operating same'20158,942,042'Nonvolatile memory device and a method of adjusting a threshold voltage of a ground selection transistor thereof'20158,638,611'Vertical nonvolatile memory devices and methods of operating same'20148,462,558'Program and erase methods for nonvolatile memory'20137,821,834'Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays'20107,813,183'Program and erase methods for nonvolatile memory'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2019Patents assigned to SAMSUNG ELECTRONICS CO LTD (14)· patent assignee history
2010–2017Based in Gyeonggi-do, KR· patent location history
2013–2017Patents assigned to SIM JAESUNG (4)· patent assignee history
2013–2014Patents assigned to CHOI JUNGDAL (2)· patent assignee history
2013Patents assigned to CHOI KIHWAN (1)· patent assignee history
2013Based in Yongin-si, KR· patent location history
2014–2019Based in Hwaseong-si, KR· patent location history
2017Patents assigned to PARK YOUNGWOO (2)· patent assignee history
2018Based in Santa Clara, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SAMSUNG ELECTRONICS CO LTD142010–2019
SIM JAESUNGself42013–2017
CHOI JUNGDAL22013–2014
PARK YOUNGWOO22017
CHOI KIHWAN12013
Locations
LocationPatentsSpan
Hwaseong-si, KR102014–2019
Gyeonggi-do, KR42010–2017
Santa Clara, California, US12018
Yongin-si, KR12013