Inventor

Richard K. Eguchi

Inventor
Austin, TX, US

Overview

33→
Patents
2001–2021
Patent span
Physics
Primary field (CPC G)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores67%
G06FElectric digital data processing26%
G01RMeasuring electric variables4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
11,056,160Non-volatile memory with selectable hard write202110,573,364Magnetic disturb diagnostic system for MRAM202010,109,356Method and apparatus for stressing a non-volatile memory20189,508,397'Non-volatile memory (NVM) with endurance control'20169,329,932'Imminent read failure detection based upon unacceptable wear for NVM cells'20169,329,921'Imminent read failure detection using high/low read voltage levels'20169,329,933'Imminent read failure detection based upon changes in error voltage windows for NVM cells'20169,318,161'Non-volatile memory robust start-up using analog-to-digital converter'20169,318,163'Robust memory start-up using clock counter'20169,224,478'Temperature-based adaptive erase or program parallelism'20159,082,510'Non-volatile memory (NVM) with adaptive write operations'20159,076,508'Built-in self trim for non-volatile memory reference current'20158,977,914'Stress-based techniques for detecting an imminent read failure in a non-volatile memory array'20158,902,667'Methods and systems for adjusting NVM cell bias conditions for program/erase operations to reduce performance degradation'20148,782,478'Non-volatile memory (NVM) with imminent error prediction'20148,687,428'Built-in self trim for non-volatile memory reference current'20148,572,445'Non-volatile memory (NVM) with imminent error prediction'20138,516,213'Method and apparatus for EEPROM emulation for preventing data loss in the event of a flash block failure'20138,509,001'Adaptive write procedures for non-volatile memory'20138,504,884'Threshold voltage techniques for detecting an imminent read failure in a memory array'20138,432,752'Adaptive write procedures for non-volatile memory using verify read'20138,427,877'Digital method to obtain the I-V curves of NVM bitcells'20138,289,773'Non-volatile memory (NVM) erase operation with brownout recovery technique'20128,095,836'Time-based techniques for detecting an imminent read failure in a memory array'20127,865,797'Memory device with adjustable read reference based on ECC and method thereof'20117,782,664'Method for electrically trimming an NVM reference cell'20107,649,782'Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor'20107,640,389'Non-volatile memory having a multiple block erase mode and method therefor'20097,599,236'In-circuit Vt distribution bit counter for non-volatile memory devices'20097,545,679'Electrical erasable programmable memory transconductance testing'20096,937,047'Integrated circuit with test pad structure and method of testing'20056,826,103'Auto-tuneable reference circuit for flash EEPROM products'20046,226,200'In-circuit memory array bit cell threshold voltage distribution measurement'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Based in Austin, TX, US· patent location history
2004–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (30)· patent assignee history
2012–2016Patents assigned to EGUCHI RICHARD K (20)· patent assignee history
2012–2015Patents assigned to HE CHEN (13)· patent assignee history
2012–2016Patents assigned to CHOY JON S (3)· patent assignee history
2013–2016Patents assigned to WEILEMANN II JON W (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FREESCALE SEMICONDUCTOR INC302004–2018
EGUCHI RICHARD Kself202012–2016
HE CHEN132012–2015
WEILEMANN II JON W52013–2016
CHOY JON S32012–2016
Locations
LocationPatentsSpan
Austin, Texas, US332001–2021