Inventor
Yu-Ling Tsai
Inventor
Hsinchu, TW
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1042%
H01LSemiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
PatentTitleYear
10,665,520Integrated circuit package and method20209,620,414'Protecting flip-chip package using pre-applied fillet'20179,064,881'Protecting flip-chip package using pre-applied fillet'20158,927,333'Die carrier for package on package assembly'20158,373,282'Wafer level chip scale package with reduced stress on solder balls'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2015Patents assigned to PU HAN-PING (3)· patent assignee history
2013–2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (3)· patent assignee history
2013–2015Patents assigned to TSAI YU-LING (3)· patent assignee history
2013–2020Based in Hsinchu, TW· patent location history
2015Patents assigned to CHEN CHEN-SHIEN (1)· patent assignee history
2017–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| PU HAN-PING | 3 | 2013–2015 |
| TAIWAN SEMICONDUCTOR MFG | 3 | 2013–2015 |
| TSAI YU-LINGself | 3 | 2013–2015 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 2 | 2017–2020 |
| CHEN CHEN-SHIEN | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 5 | 2013–2020 |