Inventor
Sarah E. Kim
Inventor
Portland, OR, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10DInorganic electric semiconductor devices9%
B82YSpecific uses or applications of nanostructures7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
F04BPositive-displacement machines for liquids4%
G11CStatic stores4%
H01GCapacitors4%
H10BElectronic memory devices4%
Y10TTechnical subjects covered by former us classification4%
PatentTitleYear
10,327,285Heating element and method for manufacturing same20198,421,225'Three-dimensional stacked substrate arrangements'20138,203,208'Three-dimensional stacked substrate arrangements'20127,973,407'Three-dimensional stacked substrate arrangements'20117,842,553'Cooling micro-channels'20107,723,208'Integrated re-combiner for electroosmotic pumps using porous frits'20107,696,015'Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips'20107,615,462'Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack'20097,576,432'Using external radiators with electroosmotic pumps for cooling integrated circuits'20097,537,954'Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same'20097,410,884'3D integrated circuits using thick metal for backside connections and offset bumps'20087,348,217'Method and structure for interfacing electronic devices'20087,274,106'Packaged electroosmotic pumps using porous frits for cooling integrated circuits'20077,271,434'Capacitor with insulating nanostructure'20077,265,406'Capacitor with conducting nanostructure'20077,244,983'Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode'20077,227,257'Cooling micro-channels'20077,183,648'Method and apparatus for low temperature copper to copper bonding'20077,157,787'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices'20077,148,565'Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack'20067,105,382'Self-aligned electrodes contained within the trenches of an electroosmotic pump'20067,105,925'Differential planarization'20067,091,084'Ultra-high capacitance device based on nanostructures'20067,084,495'Electroosmotic pumps using porous frits for cooling integrated circuit stacks'20067,063,938'Method of preparing patterned colloidal crystals'20067,056,813'Methods of forming backside connections on a wafer stack'20067,056,807'Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack'20067,037,804'Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration'20067,034,394'Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same'20066,992,381'Using external radiators with electroosmotic pumps for cooling integrated circuits'20066,981,849'Electro-osmotic pumps and micro-channels'20066,977,435'Thick metal layer integrated process flow to improve power delivery and mechanical buffering'20056,975,016'Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof'20056,943,440'Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow'20056,914,002'Differential planarization'20056,911,373'Ultra-high capacitance device based on nanostructures'20056,908,565'Etch thinning techniques for wafer-to-wafer vertical stacks'20056,897,125'Methods of forming backside connections on a wafer stack'20056,887,769'Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same'20056,870,270'Method and structure for interfacing electronic devices'20056,790,748'Thinning techniques for wafer-to-wafer vertical stacks'20046,790,780'Fabrication of 3-D capacitor with dual damascene process'20046,762,076'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices'20046,661,085'Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack'20036,645,832'Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack'20036,599,808'Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2013Patents assigned to INTEL CORP (44)· patent assignee history
2003–2013Based in Portland, OR, US· patent location history
2006–2019Based in Daejeon, KR· patent location history
2008Based in Seoul, KR· patent location history
2012–2013Patents assigned to CHAN MICHAEL Y (2)· patent assignee history
2012–2013Patents assigned to HARMES MICHAEL C (2)· patent assignee history
2012–2013Patents assigned to KIM SARAH E (2)· patent assignee history
2012–2013Patents assigned to KOBRINSKY MAURO J (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 44 | 2003–2013 |
| CHAN MICHAEL Y | 2 | 2012–2013 |
| HARMES MICHAEL C | 2 | 2012–2013 |
| KIM SARAH Eself | 2 | 2012–2013 |
| KOBRINSKY MAURO J | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 43 | 2003–2013 |
| Daejeon, KR | 2 | 2006–2019 |
| Seoul, KR | 1 | 2008 |