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Inventor

Michael P. Belyansky

Inventor
Bethel, CT, US

Overview

51→
Patents
2003–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H01LSemiconductor devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
C23CCoating metallic material2%
H05KPrinted circuits2%
H10BElectronic memory devices2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
11,107,814Vertical fin field effect transistor devices with a replacement metal gate202111,049,858Vertical fin field effect transistor devices with a replacement metal gate202111,011,624Vertical transport field-effect transistor (VFET) with dual top spacer202111,004,850Vertical fin field effect transistor devices with a replacement metal gate202110,957,781Uniform horizontal spacer202110,943,992Transistor having straight bottom spacers202110,832,973Stress modulation of nFET and pFET fin structures202010,741,663Encapsulation layer for vertical transport field-effect transistor gate stack202010,741,673Controlling gate profile by inter-layer dielectric (ILD) nanolaminates202010,734,245Highly selective dry etch process for vertical FET STI recess202010,679,993Vertical fin field effect transistor devices with a replacement metal gate202010,672,910Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)202010,665,512Stress modulation of nFET and pFET fin structures202010,586,700Protection of low temperature isolation fill202010,535,550Protection of low temperature isolation fill202010,388,766Vertical transport FET (VFET) with dual top spacer201910,249,730Controlling gate profile by inter-layer dielectric (ILD) nanolaminates201910,170,582Uniform bottom spacer for vertical field effect transistor201910,141,188Resist having tuned interface hardmask layer for EUV exposure201810,134,592Resist having tuned interface hardmask layer for EUV exposure20189,929,012'Resist having tuned interface hardmask layer for EUV exposure'20189,613,956'Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide'20179,397,002'Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide'20168,557,649'Method for controlling structure height'20138,420,542'Method of patterned image reversal'20137,863,646'Dual oxide stress liner'20117,750,410'Structure and method to improve channel mobility by gate electrode stress modification'20107,741,166'Oxidation method for altering a film structure'20107,691,701'Method of forming gate stack and structure thereof'20107,659,160'Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same'20107,648,871'Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same'20107,618,853'Field effect transistors with dielectric source drain halo regions and reduced miller capacitance'20097,585,704'Method of producing highly strained PECVD silicon nitride thin films at low temperature'20097,569,848'Mobility enhanced CMOS devices'20097,488,658'Stressed semiconductor device structures having granular semiconductor material'20097,342,266'Field effect transistors with dielectric source drain halo regions and reduced miller capacitance'20087,273,638'High density plasma oxidation'20077,271,049'Method of forming self-aligned low-k gate cap'20077,230,296'Self-aligned low-k gate cap'20077,205,206'Method of fabricating mobility enhanced CMOS devices'20077,202,516'CMOS transistor structure including film having reduced stress by exposure to atomic oxygen'20077,122,849'Stressed semiconductor device structures having granular semiconductor material'20067,081,393'Reduced dielectric constant spacer materials integration for high speed logic gates'20066,982,196'Oxidation method for altering a film structure and CMOS transistor structure formed therewith'20066,977,194'Structure and method to improve channel mobility by gate electrode stress modification'20056,967,137'Forming collar structures in deep trench capacitors with thermally stable filler material'20056,914,015'HDP process for high aspect ratio gap filling'20056,890,833'Trench isolation employing a doped oxide trench fill'20056,869,860'Filling high aspect ratio isolation structures with polysilazane based material'20056,642,147'Method of making thermally stable planarizing films'20036,562,713'Method of protecting semiconductor areas while exposing a gate'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2021Patents assigned to IBM (49)· patent assignee history
2003–2018Based in Bethel, CT, US· patent location history
2007Based in Bethal, CT, US· patent location history
2013Patents assigned to BELYANSKY MICHAEL P (2)· patent assignee history
2013Patents assigned to VENIGALLA RAJASEKHAR (2)· patent assignee history
2013Patents assigned to AMINPUR MASSUD A (1)· patent assignee history
2013Patents assigned to AQUILINO MICHAEL VINCENT (1)· patent assignee history
2013Based in Hopewell Junction, NY, US· patent location history
2016–2017Based in Clifton Park, NY, US· patent location history
2019–2021Based in Halfmoon, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM492003–2021
BELYANSKY MICHAEL Pself22013
VENIGALLA RAJASEKHAR22013
AMINPUR MASSUD A12013
AQUILINO MICHAEL VINCENT12013
Locations
LocationPatentsSpan
Bethel, CT, US272003–2018
Halfmoon, New York, US182019–2021
Clifton Park, New York, US22016–2017
Hopewell Junction, New York, US22013
Bethal, CT, US12007