Inventor

Simon Edward Willard

Inventor

Irvine, CA, US

Overview

33→

Patents

2001–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices29%

H10DInorganic electric semiconductor devices27%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%

H03FAmplifiers10%

H03KPulse technique8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

G11CStatic stores1%

PatentTitleYear

11,049,855Tunable capacitive compensation for RF switch FET stacks2021 11,018,662AC coupling modules for bias ladders2021 10,985,183Butted body contact for SOI transistor2021 10,971,359Managed substrate effects for stabilized SOI FETs2021 10,923,592High voltage switching device2021 10,886,911Stacked FET switch bias ladders2021 10,862,473Positive logic switch with selectable DC blocking circuit2020 10,784,818Body tie optimization for stacked transistor amplifier2020 10,770,480Systems, methods, and apparatus for enabling high voltage circuits2020 10,763,257S-contact for SOI2020 10,756,166Low leakage FET2020 10,700,642Gate drivers for stacked transistor amplifiers2020 10,672,726Transient stabilized SOI FETs2020 10,630,280AC coupling modules for bias ladders2020 10,629,621Butted body contact for SOI transistor2020 10,546,747Managed substrate effects for stabilized SOI FETs2020 10,505,530Positive logic switch with selectable DC blocking circuit2019 10,475,720S-contact thermal structure with active circuitry2019 10,438,950S-contact for SOI2019 10,389,306Gate drivers for stacked transistor amplifiers2019 10,367,453Body tie optimization for stacked transistor amplifier2019 10,319,854High voltage switching device2019 10,276,371Managed substrate effects for stabilized SOI FETs2019 10,236,872AC coupling modules for bias ladders2019 10,192,884Butted body contact for SOI transistor2019 10,147,740Methods and structures for reducing back gate effect in a semiconductor device2018 10,115,787Low leakage FET2018 9,882,531'Body tie optimization for stacked transistor amplifier'2018 9,847,348Systems, methods and apparatus for enabling high voltage circuits2017 9,842,858'Butted body contact for SOI transistor'2017 9,843,293'Gate drivers for stacked transistor amplifiers'2017 9,837,412S-contact for SOI2017 6,175,261'Fuse cell for on-chip trimming'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001Patents assigned to TEXAS INSTRUMENTS INC (1)· patent assignee history

2001–2021Based in Irvine, CA, US· patent location history

2017–2018Patents assigned to PEREGRINE SEMICONDUCTOR CORP (5)· patent assignee history

2018–2021Patents assigned to PSEMI CORP (27)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
PSEMI CORP	27	2018–2021
PEREGRINE SEMICONDUCTOR CORP	5	2017–2018
TEXAS INSTRUMENTS INC	1	2001

Locations

Location	Patents	Span
Irvine, California, US	33	2001–2021