Inventor
Heap Hoe Kuan
Inventor
Singapore, SG
Overview
Patents· 144 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1059%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H01LSemiconductor devices10%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H05KPrinted circuits2%
H10DInorganic electric semiconductor devices2%
B29CShaping or joining of plastics0%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems0%
Y10TTechnical subjects covered by former us classification0%
PatentTitleYear
11,031,376Chip package and method of forming the same202110,217,873Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus20199,847,253Package-on-package using through-hole via die on saw streets20179,564,413'Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus'20179,553,162'Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus'20179,524,938'Package-in-package using through-hole via die on saw streets'20169,524,955'Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure'20169,515,016'Semiconductor package and method of forming z-direction conductive posts embedded in structurally protective encapsulant'20169,406,647'Extended redistribution layers bumped wafer'20169,299,648'Integrated circuit packaging system with patterned substrate and method of manufacture thereof'20169,293,350'Semiconductor package system with cavity substrate and manufacturing method therefor'20169,275,877'Semiconductor device and method of forming semiconductor package using panel form carrier'20169,257,356'Semiconductor device and method of forming an IPD beneath a semiconductor die with direct connection to external devices'20169,177,848'Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer'20159,123,733'Integrated circuit packaging system with package underfill and method of manufacture thereof'20159,099,455'Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant'20159,064,876'Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP'20159,059,186'Embedded semiconductor die package and method of making the same using metal frame carrier'20159,048,197'Integrated circuit package system employing wafer level chip scale packaging'20159,030,006'Integrated circuit package system with internal stacking module'20159,029,205'Integrated circuit packaging system having planar interconnect and method for manufacture thereof'20159,006,882'Semiconductor device and method of forming recessed conductive vias in saw streets'20158,963,309'Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof'20158,957,530'Integrated circuit packaging system with embedded circuitry and post'20158,878,361'Leadless package system having external contacts'20148,852,986'Integrated circuit package system employing resilient member mold system technology'20148,815,643'Method of fabricating semiconductor die with through-hole via on saw streets and through-hole via in active area of die'20148,803,330'Integrated circuit package system with mounting structure'20148,759,954'Integrated circuit package system with offset stacked die'20148,723,305'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20148,716,853'Extended redistribution layers bumped wafer'20148,659,113'Embedded semiconductor die package and method of making the same using metal frame carrier'20148,648,448'Semiconductor device and method of shielding semiconductor die from inter-device interference'20148,642,382'Integrated circuit packaging system with support structure and method of manufacture thereof'20148,624,364'Integrated circuit packaging system with encapsulation connector and method of manufacture thereof'20148,604,602'Integrated circuit packaging system with reinforced encapsulant having embedded interconnect and method of manufacture thereof'20138,592,286'Ultra-thin wafer system and method of manufacture thereof'20138,546,195'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20138,536,692'Mountable integrated circuit package system with mountable integrated circuit die'20138,513,542'Integrated circuit leaded stacked package system'20138,507,319'Integrated circuit package system with shield'20138,492,204'Integrated circuit package-in-package system with wire-in-film encapsulant and method for manufacturing thereof'20138,487,434'Integrated circuit package system with redistribution layer and method for manufacturing thereof'20138,476,120'Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors'20138,445,325'Package-in-package using through-hole via die on saw streets'20138,421,202'Integrated circuit packaging system with flex tape and method of manufacture thereof'20138,421,197'Integrated circuit package system with warp-free chip'20138,420,950'Circuit system with leads and method of manufacture thereof'20138,409,921'Integrated circuit package system including honeycomb molding'20138,405,228'Integrated circuit packaging system with package underfill and method of manufacture thereof'20138,390,108'Integrated circuit packaging system with stacking interconnect and method of manufacture thereof'20138,378,502'Integrated circuit package system with image sensor system'20138,368,188'Drop-mold conformable material as an encapsulation for an integrated circuit package system and method for manufacturing thereof'20138,368,199'Integrated circuit package system for stackable devices and method for manufacturing thereof'20138,354,304'Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant'20138,354,746'Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant'20138,334,150'Wafer level laser marking system for ultra-thin wafers using support tape'20128,309,451'Semiconductor device and method of providing common voltage bus and wire bondable redistribution'20128,304,880'Integrated circuit packaging system with package-on-package and method of manufacture thereof'20128,299,596'Integrated circuit packaging system with bump conductors and method of manufacture thereof'20128,288,844'Integrated circuit packaging system with package stacking and method of manufacture thereof'20128,278,141'Integrated circuit package system with internal stacking module'20128,269,320'Integrated circuit package system for electromagnetic isolation and method for manufacturing thereof'20128,263,434'Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP'20128,258,015'Integrated circuit package system with penetrable film adhesive'20128,258,612'Encapsulant interposer system with integrated passive devices and manufacturing method therefor'20128,247,268'Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer'20128,232,658'Stackable integrated circuit package system with multiple interconnect interface'20128,222,717'Embedded semiconductor die package and method of making the same using metal frame carrier'20128,188,586'Mountable integrated circuit package system with mounting interconnects'20128,183,675'Integrated circuit package-on-package system with anti-mold flash feature'20128,178,956'Integrated circuit package system for shielding electromagnetic interference'20128,164,172'Integrated circuit package in package system'20128,163,597'Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure'20128,159,047'Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors'20128,143,711'Integrated circuit package system with offset stacking and anti-flash structure'20128,138,024'Package system for shielding semiconductor dies from electromagnetic interference'20128,138,590'Integrated circuit package system with wire-in-film encapsulation'20128,124,460'Integrated circuit package system employing an exposed thermally conductive coating'20128,124,455'Wafer strength reinforcement system for ultra thin wafer thinning'20128,106,500'Stackable integrated circuit package system'20128,101,460'Semiconductor device and method of shielding semiconductor die from inter-device interference'20128,084,849'Integrated circuit package system with offset stacking'20118,084,302'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20118,080,882'Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device'20118,080,885'Integrated circuit packaging system with multi level contact and method of manufacture thereof'20118,062,929'Semiconductor device and method of stacking same size semiconductor die electrically connected through conductive via formed around periphery of the die'20118,048,776'Semiconductor device and method of supporting a wafer during backgrinding and reflow of solder bumps'20118,049,314'Integrated circuit package system with insulator over circuitry'20118,039,311'Leadless semiconductor chip carrier system'20118,021,923'Semiconductor package having through-hole vias on saw streets formed with partial saw'20118,017,521'Semiconductor package having through-hole vias on saw streets formed with partial saw'20118,017,501'Semiconductor package having through-hole vias on saw streets formed with partial saw'20118,018,041'Integrated circuit package system with offset stacked die'20117,993,941'Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant'20117,993,979'Leadless package system having external contacts'20117,989,270'Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors'20117,989,269'Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof'20117,986,043'Integrated circuit package on package system'20117,985,628'Integrated circuit package system with interconnect lock'20117,981,702'Integrated circuit package in package system'20117,968,996'Integrated circuit package system with supported stacked die'20117,960,841'Through-hole via on saw streets'20117,948,066'Integrated circuit package system with lead locking structure'20117,939,368'Wafer level chip scale package system with a thermal dissipation structure'20117,923,846'Integrated circuit package-in-package system with wire-in-film encapsulant'20117,911,070'Integrated circuit packaging system having planar interconnect'20117,902,638'Semiconductor die with through-hole via on saw streets and through-hole via in active area of die'20117,902,644'Integrated circuit package system for electromagnetic isolation'20117,892,894'Method of manufacturing integrated circuit package system with warp-free chip'20117,888,184'Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof'20117,872,345'Integrated circuit package system with rigid locking lead'20117,868,434'Integrated circuit package-on-package stacking system'20117,863,109'Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof'20117,859,094'Integrated circuit package system for stackable devices'20107,843,042'Wafer level integration package'20107,842,542'Embedded semiconductor die package and method of making the same using metal frame carrier'20107,843,047'Encapsulant interposer system with integrated passive devices and manufacturing method therefor'20107,838,899'Integrated circuit package system with image sensor system'20107,834,430'Drop-mold conformable material as an encapsulation for an integrated circuit package system'20107,829,984'Integrated circuit package system stackable devices'20107,829,998'Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer'20107,812,449'Integrated circuit package system with redistribution layer'20107,781,261'Integrated circuit package system with offset stacking and anti-flash structure'20107,768,125'Multi-chip package system'20107,750,452'Same size die stacked package having through-hole vias formed in organic material'20107,741,707'Stackable integrated circuit package system'20107,732,252'Multi-chip package system incorporating an internal stacking module with support protrusions'20107,727,816'Integrated circuit package system with offset stacked die'20107,723,159'Package-on-package using through-hole via die on saw streets'20107,723,146'Integrated circuit package system with image sensor system'20107,718,472'Integrated circuit package-on-package stacking system and method of manufacture thereof'20107,709,944'Integrated circuit package system with package integration'20107,704,796'Semiconductor device and method of forming recessed conductive vias in saw streets'20107,700,458'Integrated circuit package system employing wafer level chip scale packaging'20107,687,318'Extended redistribution layers bumped wafer'20107,659,145'Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device'20107,618,848'Integrated circuit package system with supported stacked die'20097,585,750'Semiconductor package having through-hole via on saw streets formed with partial saw'20097,569,421'Through-hole via on saw streets'20097,566,966'Integrated circuit package-on-package system with anti-mold flash feature'20097,553,752'Method of making a wafer level integration package'20097,535,086'Integrated circuit package-on-package stacking system'20097,385,299'Stackable integrated circuit package system with multiple interconnect interface'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2017Patents assigned to STATS CHIPPAC LTD (139)· patent assignee history
2008–2019Based in Singapore, SG· patent location history
2011–2017Patents assigned to KUAN HEAP HOE (78)· patent assignee history
2011–2017Patents assigned to CHOW SENG GUAN (55)· patent assignee history
2011–2016Patents assigned to HUANG RUI (36)· patent assignee history
2011–2017Patents assigned to DO BYUNG TAI (30)· patent assignee history
2021Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| STATS CHIPPAC LTD | 139 | 2008–2017 |
| KUAN HEAP HOEself | 78 | 2011–2017 |
| CHOW SENG GUAN | 55 | 2011–2017 |
| HUANG RUI | 36 | 2011–2016 |
| DO BYUNG TAI | 30 | 2011–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 143 | 2008–2019 |
| Hsinchu, TW | 1 | 2021 |