Inventor
CHENG-TA WU
Inventor
TW
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10DInorganic electric semiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%
H01JElectric discharge tubes or discharge lamps2%
H10BElectronic memory devices1%
G07CTime or attendance registers1%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
H04BTransmission1%
PatentTitleYear
12,586,434System and method for detecting people entering and leaving field202612,456,618Semiconductor-on-insulator (SOI) substrate and method for forming202512,396,222RFSOI semiconductor structures including a nitrogen-doped charge-trapping layer and methods of manufacturing the same202512,364,048Conductive contact for ion through-substrate via202512,336,217Flat STI surface for gate oxide uniformity in Fin FET devices202512,211,877Back-side deep trench isolation structure for image sensor202512,183,804RF switch device with a sidewall spacer having a low dielectric constant202412,165,911Method for forming a semiconductor-on-insulator (SOI) substrate202412,148,756Selective polysilicon growth for deep trench polysilicon isolation structure202412,119,267Method for manufacturing semiconductor structure202412,100,767Strained gate semiconductor device having an interlayer dielectric doped with large species material202412,087,206Color adjustment device, display and color adjustment method202412,074,036Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer202412,062,539Semiconductor-on-insulator (SOI) substrate and method for forming202412,040,221Fabrication method of metal-free SOI wafer202411,984,477RFSOI semiconductor structures including a nitrogen-doped charge-trapping layer and methods of manufacturing the same202411,955,496Back-side deep trench isolation structure for image sensor202411,929,379Conductive contact for ion through-substrate via202411,923,235Method for forming semiconductor device having isolation structures with different thicknesses202411,901,435RF switch device with a sidewall spacer having a low dielectric constant202411,855,159Method for forming thin semiconductor-on-insulator (SOI) substrates202311,830,764Method for forming a semiconductor-on-insulator (SOI) substrate202311,710,656Method of forming semiconductor-on-insulator (SOI) substrate202311,705,328Semiconductor-on-insulator (SOI) substrate and method for forming202311,611,005Backside illuminated photo-sensitive device with gradated buffer layer202311,610,808Semiconductor wafer with low defect count and method for manufacturing thereof202311,594,597Selective polysilicon growth for deep trench polysilicon isolation structure202311,551,979Method for manufacturing semiconductor structure202311,495,489Method for forming a semiconductor-on-insulator (SOI) substrate202211,450,555Method for forming semiconductor device having isolation structures with different thicknesses202211,398,516Conductive contact for ion through-substrate via202211,362,176RFSOI semiconductor structures including a nitrogen-doped charge-trapping layer and methods of manufacturing the same202211,329,160FinFET gate structure202211,296,209RF switch device with a sidewall spacer having a low dielectric constant202211,289,330Semiconductor-on-insulator (SOI) substrate and method for forming202211,271,114Strained gate semiconductor device with oxygen-doped interlayer dielectric material202211,264,469Method for forming thin semiconductor-on-insulator (SOI) substrates202211,232,974Fabrication method of metal-free SOI wafer202211,164,945SOI substrate, semiconductor device and method for manufacturing the same202111,158,534SOI substrate2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (38)· patent assignee history
2021–2026Based in TW· patent location history
2024Patents assigned to WISTRON CORP (1)· patent assignee history
2026Patents assigned to QUANTA COMP INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 38 | 2021–2025 |
| QUANTA COMP INC | 1 | 2026 |
| WISTRON CORP | 1 | 2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 40 | 2021–2026 |