Inventor
Thomas Hoffmann
Inventor
Los Gatos, CA, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
H01LSemiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10BElectronic memory devices7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
A61KPreparations for medical, dental or toiletry purposes1%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations1%
C07DHeterocyclic compounds1%
PatentTitleYear
11,078,168Substituted N-hydroxyamidinoheterocycles as modulators of indoleamine 2,3-dioxygenase202110,217,838Semiconductor structure with multiple transistors having various threshold voltages201910,014,387Semiconductor structure with multiple transistors having various threshold voltages20189,893,148'Method for fabricating a transistor device with a tuned dopant profile'20189,812,550'Semiconductor structure with multiple transistors having various threshold voltages'20179,577,041'Method for fabricating a transistor device with a tuned dopant profile'20179,508,728'CMOS gate stack structures and processes'20169,406,567'Method for fabricating multiple transistor devices on a substrate with varying threshold voltages'20169,391,076'CMOS structures and processes based on selective thinning'20169,368,624'Method for fabricating a transistor with reduced junction leakage current'20169,299,698'Semiconductor structure with multiple transistors having various threshold voltages'20169,299,801'Method for fabricating a transistor device with a tuned dopant profile'20169,281,248'CMOS gate stack structures and processes'20169,196,727'High uniformity screen and epitaxial layers for CMOS devices'20159,105,711'Semiconductor structure with reduced junction leakage and method of fabrication thereof'20159,054,219'Semiconductor devices having fin structures and fabrication methods thereof'20159,041,126'Deeply depleted MOS transistors having a screening layer and methods thereof'20158,916,937'Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer'20148,883,600'Transistor having reduced junction leakage and methods of forming thereof'20148,735,987'CMOS gate stack structures and processes'20148,653,604'Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer'20148,637,955'Semiconductor structure with reduced junction leakage and method of fabrication thereof'20148,629,016'Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer'20148,614,128'CMOS structures and processes based on selective thinning'20138,012,827'Method for fabricating a dual workfunction semiconductor device and the device made thereof'20117,973,333'Lateral DMOS transistor and method for the production thereof'20117,972,947'Method for fabricating a semiconductor element, and semiconductor element'20117,851,326'Method for producing deep trench structures'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2011Based in Filderstadt, DE· patent location history
2011Based in Leuven, BE· patent location history
2013–2015Patents assigned to SUVOLTA INC (9)· patent assignee history
2013–2016Patents assigned to HOFFMANN THOMAS (6)· patent assignee history
2013–2016Patents assigned to RANADE PUSHKAR (6)· patent assignee history
2013–2016Patents assigned to THOMPSON SCOTT E (5)· patent assignee history
2013–2019Based in Los Gatos, CA, US· patent location history
2014–2016Based in San Jose, CA, US· patent location history
2015–2019Patents assigned to MIE FUJITSU SEMICONDUCTOR LTD (16)· patent assignee history
2021Based in Speyer, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MIE FUJITSU SEMICONDUCTOR LTD | 16 | 2015–2019 |
| SUVOLTA INC | 9 | 2013–2015 |
| HOFFMANN THOMASself | 6 | 2013–2016 |
| RANADE PUSHKAR | 6 | 2013–2016 |
| THOMPSON SCOTT E | 5 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 20 | 2013–2019 |
| San Jose, California, US | 3 | 2014–2016 |
| Leuven, BE | 2 | 2011 |
| Filderstadt, DE | 2 | 2010–2011 |
| Speyer, DE | 1 | 2021 |