Inventor
Christopher S. Blair
Inventor
San Jose, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices45%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H01LSemiconductor devices8%
PatentTitleYear
9,673,316'Vertical semiconductor device having frontside interconnections'20179,209,091'Integrated monolithic galvanic isolator'20158,963,281'Simultaneous isolation trench and handle wafer contact formation'20158,624,349'Simultaneous isolation trench and handle wafer contact formation'20146,303,503'Process for the formation of cobalt salicide layers employing a sputter etch surface preparation step'20016,171,901'Process for forming silicided capacitor utilizing oxidation barrier layer'20016,136,705'Self-aligned dual thickness cobalt silicide layer formation process'20006,103,610'Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture'20006,040,606'Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture'20005,998,873'Low contact resistance and low junction leakage metal interconnect contact structure'19995,925,923'Merged single polysilicon bipolar NPN transistor'19995,904,536'Self aligned poly emitter bipolar technology using damascene technique'19995,882,976'Method of fabricating a self-aligned double polysilicon NPN transistor with poly etch stop'19995,661,046'Method of fabricating BiCMOS device'19975,451,546'Masking method used in salicide process for improved yield by preventing damage to oxide spacers'19955,338,696'Method of fabricating BiCMOS device'19945,338,694'Method of fabricating BiCMOS device'19945,242,854'High performance semiconductor devices and their manufacture'19935,139,961'Reducing base resistance of a BJT by forming a self aligned silicide in the single crystal region of the extrinsic base'19925,045,483'Self-aligned silicided base bipolar transistor and resistor and method of fabrication'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2001Patents assigned to NAT SEMICONDUCTOR CORP (16)· patent assignee history
1991–1997Based in Puyallup, WA, US· patent location history
1995–2001Based in San Jose, CA, US· patent location history
2014–2017Patents assigned to MAXIM INTEGRATED PRODUCTS (4)· patent assignee history
2014–2015Patents assigned to BLAIR CHRISTOPHER S (2)· patent assignee history
2014–2017Based in Lake Oswego, OR, US· patent location history
2015Patents assigned to BOUCHE GUILLAUME (1)· patent assignee history
2015Patents assigned to HARPER DAVID (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 16 | 1991–2001 |
| MAXIM INTEGRATED PRODUCTS | 4 | 2014–2017 |
| BLAIR CHRISTOPHER Sself | 2 | 2014–2015 |
| BOUCHE GUILLAUME | 1 | 2015 |
| HARPER DAVID | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 10 | 1995–2001 |
| Puyallup, Washington, US | 6 | 1991–1997 |
| Lake Oswego, OR, US | 4 | 2014–2017 |