Inventor

In-Seak Hwang

Inventor
Suwon-si, KR

Overview

41→
Patents
2000–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 41 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10BElectronic memory devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H01LSemiconductor devices9%
C11DDetergent compositions4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H01JElectric discharge tubes or discharge lamps2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B01FMixing, e.g. dissolving, emulsifying or dispersing1%
PatentTitleYear
10,438,799Methods of fabricating semiconductor devices including support patterns201910,109,529Semiconductor device and method of manufacturing the same20189,985,106Semiconductor devices utilizing spacer structures20189,960,169Methods of manufacturing semiconductor devices20189,659,940'Semiconductor device and method of manufacturing the same'20179,390,961'Semiconductor devices having plug insulators'20169,269,720'Methods of fabricating semiconductor devices'20169,240,414'Semiconductor devices having self-aligned contact pads'20169,184,227'Methods of manufacturing semiconductor devices having self-aligned contact pads'20158,962,455'Method of fabricating semiconductor device'20158,748,254'Method of manufacturing semiconductor device'20148,723,297'Memory device'20148,662,958'Chemical-mechanical polishing apparatus for manufacturing semiconductor devices'20148,604,550'Semiconductor devices including gate structure and method of fabricating the same'20138,551,288'Apparatus and method for removing a photoresist structure from a substrate'20138,058,128'Methods of fabricating recessed channel metal oxide semiconductor (MOS) transistors'20117,573,132'Wiring structure of a semiconductor device and method of forming the same'20097,405,164'Apparatus and method for removing a photoresist structure from a substrate'20087,361,547'Method for forming a capacitor for use in a semiconductor device'20087,338,610'Etching method for manufacturing semiconductor device'20087,025,493'Chemical supply system and chemical mixing apparatus'20067,008,755'Method for forming a planarized layer of a semiconductor device'20066,946,431'Cleaning solution including aqueous ammonia solution, acetic acid and deionized water for integrated circuit devices and methods of cleaning integrated circuit devices using the same'20056,943,081'Method of forming storage nodes comprising a base in a contact hole and related structures'20056,911,364'One-cylinder stack capacitor and method for fabricating the same'20056,889,447'Method for drying a wafer and apparatus for performing the same'20056,875,706'Cleaning solution and method of cleaning a semiconductor device using the same'20056,838,330'Method of forming a contact hole of a semiconductor device'20056,837,943'Method and apparatus for cleaning a semiconductor substrate'20056,831,012'Method for forming a silicide film of a semiconductor device'20046,802,911'Method for cleaning damaged layers and polymer residue from semiconductor device'20046,717,231'Trench isolation regions having recess-inhibiting layers therein that protect against overetching'20046,706,633'Method of forming a self-aligned contact pad for use in a semiconductor device'20046,699,773'Shallow trench isolation type semiconductor device and method of forming the same'20046,700,153'One-cylinder stack capacitor and method for fabricating the same'20046,548,853'Cylindrical capacitors having a stepped sidewall and methods for fabricating the same'20036,500,726'Shallow trench isolation type semiconductor device and method of forming the same'20026,461,937'Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching'20026,369,008'Cleaning solutions for removing contaminants from the surfaces of semiconductor substrates and cleaning methods using the same'20026,331,478'Methods for manufacturing semiconductor devices having chamfered metal silicide layers'20016,146,994'Method for forming self-aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2019Patents assigned to SAMSUNG ELECTRONICS CO LTD (41)· patent assignee history
2000–2008Based in Kyungki-do, KR· patent location history
2001–2019Based in Suwon-si, KR· patent location history
2005Based in Gyeonggi-do, KR· patent location history
2011–2016Patents assigned to HWANG IN-SEAK (8)· patent assignee history
2013–2014Patents assigned to CHUNG DAE-HYUK (2)· patent assignee history
2015–2016Patents assigned to IM KI-VIN (2)· patent assignee history
2015–2016Patents assigned to KIM YOUNG-KUK (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SAMSUNG ELECTRONICS CO LTD412000–2019
HWANG IN-SEAKself82011–2016
CHUNG DAE-HYUK22013–2014
IM KI-VIN22015–2016
KIM YOUNG-KUK22015–2016
Locations
LocationPatentsSpan
Suwon-si, KR322001–2019
Kyungki-do, KR62000–2008
Gyeonggi-do, KR32005