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Inventor

Boaz Eitan

Inventor
Ra'anana, IL

Overview

122→
Patents
1984–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 122 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores38%
H10DInorganic electric semiconductor devices22%
H10BElectronic memory devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H03KPulse technique2%
A61MDevices for introducing media into, or onto, the body2%
H02JElectric power networks1%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
A61NElectrotherapy0%
PatentTitleYear
11,033,681Automatic catheter recognition and associated methods, systems and circuits202110,894,131Methods circuits devices assemblies systems and associated computer executable code for sensing and analyzing fluid characteristics within a conduit of a medical device and air bubbles20219,726,167'Methods, circuits, devices, apparatuses, encasements and systems for identifying if a medical infusion system is decalibrated'20179,674,811'Methods, apparatus and systems for medical device communication, control and localization'20179,490,261'Minimizing disturbs in dense non volatile memory arrays'20169,457,158'Air trap for intravenous pump'20168,208,300'Non-volatile memory cell with injector'20128,189,397'Retention in NVM with top or bottom injection'20128,116,142'Method and circuit for erasing a non-volatile memory cell'20128,106,442'NROM fabrication method'20128,008,709'NROM fabrication method'20117,964,459'Non-volatile memory structure and method of fabrication'20117,943,979'NROM fabrication method'20117,864,612'Reading array cell with matched reference cell'20117,808,818'Secondary injection for NROM'20107,804,126'Dense non-volatile memory array and method of fabrication'20107,786,512'Dense non-volatile memory array and method of fabrication'20107,760,554'NROM non-volatile memory and mode of operation'20107,738,304'Multiple use memory chip'20107,701,779'Method for programming a reference cell'20107,692,961'Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection'20107,668,017'Method of erasing non-volatile memory cells'20107,652,930'Method, circuit and system for erasing one or more non-volatile memory cells'20107,638,835'Double density NROM with nitride strips (DDNS)'20097,638,850'Non-volatile memory structure and method of fabrication'20097,573,745'Multiple use memory chip'20097,518,908'EEPROM array and method for operation thereof'20097,512,009'Method for programming a reference cell'20097,489,562'Multiple use memory chip'20097,457,183'Operating array cells with matched reference cells'20087,420,848'Method, system, and circuit for operating a non-volatile memory array'20087,405,969'Non-volatile memory cell and non-volatile memory devices'20087,400,529'Non-volatile memory cell and non-volatile memory device using said cell'20087,317,633'Protection of NROM devices from charge damage'20087,257,025'Method for reading non-volatile memory cells'20077,190,620'Method for operating a memory device'20077,136,304'Method, system and circuit for programming a non-volatile memory array'20067,123,532'Operating array cells with matched reference cells'20067,116,577'Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping'20067,079,420'Method for operating a memory device'20067,064,983'Method for programming a reference cell'20066,954,382'Multiple use memory chip'20056,954,393'Reading array cell with matched reference cell'20056,937,521'Programming and erasing methods for a non-volatile memory cell'20056,928,001'Programming and erasing methods for a non-volatile memory cell'20056,917,544'Multiple use memory chip'20056,888,757'Method for erasing a memory cell'20056,885,585'NROM NOR array'20056,828,625'Protective layer in memory device and method therefor'20046,829,172'Programming of nonvolatile memory cells'20046,803,279'NROM fabrication method'20046,803,299'Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping'20046,768,165'Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping'20046,704,217'Symmetric segmented memory array architecture'20046,700,818'Method for operating a memory device'20046,664,588'NROM cell with self-aligned programming and erasure areas'20036,649,972'Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping'20036,643,181'Method for erasing a memory cell'20036,636,440'Method for operation of an EEPROM array, including refresh thereof'20036,633,496'Symmetric architecture for memory cells having widely spread metal bit lines'20036,633,499'Method for reducing voltage drops in symmetric array architectures'20036,627,555'Method and circuit for minimizing the charging effect during manufacture of semiconductor devices'20036,614,692'EEPROM array and method for operation thereof'20036,584,017'Method for programming a reference cell'20036,583,007'Reducing secondary injection effects'20036,566,699'Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping'20036,552,387'Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping'20036,535,434'Architecture and scheme for a non-strobed read sequence'20036,490,204'Programming and erasing methods for a reference cell of an NROM array'20026,477,084'NROM cell with improved programming, erasing and cycling'20026,430,077'Method for regulating read voltage level at the drain of a cell in a symmetric array'20026,429,063'NROM cell with generally decoupled primary and secondary injection'20026,396,741'Programming of nonvolatile memory cells'20026,348,711'NROM cell with self-aligned programming and erasure areas'20026,337,502'Method and circuit for minimizing the charging effect during manufacture of semiconductor devices'20026,335,874'Symmetric segmented memory array architecture'20026,292,394'Method for programming of a semiconductor memory cell'20016,285,574'Symmetric segmented memory array architecture'20016,233,180'Device for determining the validity of word line conditions and for delaying data sensing operation'20016,215,148'NROM cell with improved programming, erasing and cycling'20016,201,282'Two bit ROM cell and process for producing same'20016,133,095'Method for creating diffusion areas for sources and drains without an etch step'20006,134,156'Method for initiating a retrieval procedure in virtual ground arrays'20006,128,226'Method and apparatus for operating with a close to ground signal'20006,118,267'Apparatus for switching a reference voltage between high and low impedance states'20006,030,871'Process for producing two bit ROM cell utilizing angled implant'20006,011,725'Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping'20005,966,603'NROM fabrication method with a periphery portion'19995,963,465'Symmetric segmented memory array architecture'19995,910,016'Scalable EPROM array'19995,886,561'Backup battery switch'19995,862,076'Fast EPROM array'19995,838,046'Operating method for ROM array which minimizes band-to-band tunneling'19985,834,859'Battery backed configurable output buffer'19985,796,313'Low power programmable ring oscillator'19985,783,964'Backup battery switch with first power up control'19985,768,192'Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping'19985,732,015'SRAM with a programmable reference voltage'19985,696,730'First read cycle circuit for semiconductor memory'19975,682,353'Self adjusting sense amplifier clock delay circuit'19975,623,443'Scalable EPROM array with thick and thin non-field oxide gate insulators'19975,568,085'Unit for stabilizing voltage on a capacitive node'19965,557,229'Apparatus and method for producing an output signal from a memory array'19965,453,636'MOS SRAM cell with open base bipolar loads'19955,432,730'Electrically programmable read only memory array'19955,321,660'Structure and method for compensating for programming threshold shift due to neighbor effect in an array'19945,204,835'EPROM virtual ground array'19935,151,375'EPROM virtual ground array'19925,042,009'Method for programming a floating gate memory device'19915,034,786'Opaque cover for preventing erasure of an EPROM'19915,021,847'Split gate memory array having staggered floating gate rows and method for making same'19915,014,097'On-chip high voltage generator and regulator in an integrated circuit'19915,006,974'On-chip high voltage generator and regulator in an integrated circuit'19914,998,220'EEPROM with improved erase structure'19914,868,629'Self-aligned split gate EPROM'19894,795,719'Self-aligned split gate eprom process'19894,763,184'Input circuit for protecting against damage caused by electrostatic discharge'19884,758,869'Nonvolatile floating gate transistor structure'19884,649,520'Single layer polycrystalline floating gate'19874,639,893'Self-aligned split gate EPROM'19874,577,295'Hybrid E.sup.2 cell and related array'19864,432,075'Electrically programmable non-volatile memory'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1984–1999Based in Sunnyvale, CA, US· patent location history
1987–1999Patents assigned to WAFERSCALE INTEGRATION INC (30)· patent assignee history
1995–2012Based in Ra'anana, IL· patent location history
1995Based in Ranana, IL· patent location history
1998–2010Patents assigned to SAIFUN SEMICONDUCTORS LTD (73)· patent assignee history
2000–2002Patents assigned to TOWER SEMICONDUCTORS LTD (5)· patent assignee history
2005–2006Based in Ra′anana, IL· patent location history
2009–2021Based in Hofit, IL· patent location history
2011–2012Patents assigned to Spansion Israel Ltd (8)· patent assignee history
2012–2017Patents assigned to EITAN BOAZ (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SAIFUN SEMICONDUCTORS LTD731998–2010
WAFERSCALE INTEGRATION INC301987–1999
EITAN BOAZself82012–2017
Spansion Israel Ltd82011–2012
TOWER SEMICONDUCTORS LTD52000–2002
Locations
LocationPatentsSpan
Ra'anana, IL861995–2012
Sunnyvale, California, US191984–1999
Hofit, IL142009–2021
Ra′anana, IL22005–2006
Ranana, IL11995