Inventor

Travis R. Hebig

Inventor

Rochester, MN, US

Overview

2009–2018

Patent span

Physics

Primary field (CPC G)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores38%

G06FElectric digital data processing10%

H03KPulse technique10%

C08JWorking-up4%

C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients4%

C08LCompositions of macromolecular compounds4%

G01NInvestigating or analysing materials by determining their chemical or physical properties4%

H10DInorganic electric semiconductor devices4%

H01LSemiconductor devices3%

B01DSeparation2%

PatentTitleYear

9,959,926Method and apparatus for selective write assist using shared boost capacitor2018 9,908,989'Recyclate verification'2018 9,902,625'Removal of HAB-produced toxins from bodies of water'2018 9,783,645'Recyclate verification'2017 9,778,244'Recyclate verification'2017 9,753,667'High bandwidth memory and glitch-less differential XOR'2017 9,714,177'Removal of HAB-produced toxins from bodies of water'2017 9,708,463'Recyclate verification'2017 9,542,981'Self-timed, single-ended sense amplifier'2017 9,384,835'Content addressable memory early-predict late-correct single ended sensing'2016 9,335,367'Implementing low temperature wafer test'2016 9,315,619'Binding Bisphenol A in a polycarbonate container'2016 9,317,802'Detecting water intrusion in electronic devices'2016 9,312,858'Level shifter for a time-varying input'2016 9,299,451'Tamper resistant electronic system utilizing acceptable tamper threshold count'2016 9,287,873'Level shifter for a time-varying input'2016 9,281,023'Single ended sensing circuits for signal lines'2016 9,218,880'Partial update in a ternary content addressable memory'2015 9,196,671'Integrated decoupling capacitor utilizing through-silicon via'2015 9,153,638'Integrated decoupling capacitor utilizing through-silicon via'2015 9,142,560'Layout to minimize FET variation in small dimension photolithography'2015 9,087,563'SRAM local evaluation and write logic for column selection'2015 9,088,277'Leakage reduction in output driver circuits'2015 9,082,484'Partial update in a ternary content addressable memory'2015 9,058,861'Power management SRAM write bit line drive circuit'2015 9,058,866'SRAM local evaluation logic for column selection'2015 8,929,116'Two phase search content addressable memory with power-gated main-search'2015 8,860,141'Layout to minimize FET variation in small dimension photolithography'2014 8,848,414'Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system'2014 8,842,487'Power management domino SRAM bit line discharge circuit'2014 8,824,196'Single cycle data copy for two-port SRAM'2014 8,754,691'Memory array pulse width control'2014 8,711,606'Data security for dynamic random access memory using body bias to clear data at power-up'2014 8,675,427'Implementing RC and coupling delay correction for SRAM'2014 8,669,800'Implementing power saving self powering down latch structure'2014 8,578,304'Implementing mulitple mask lithography timing variation mitigation'2013 8,520,429'Data dependent SRAM write assist'2013 8,467,230'Data security for dynamic random access memory using body bias to clear data at power-up'2013 8,467,261'Implementing smart switched decoupling capacitors to efficiently reduce power supply noise'2013 8,451,668'Implementing column redundancy steering for memories with wordline repowering'2013 8,427,894'Implementing single bit redundancy for dynamic SRAM circuit with any bit decode'2013 8,395,963'Data security for dynamic random access memory at power-up'2013 8,344,782'Method and apparatus to limit circuit delay dependence on voltage for single phase transition'2013 8,159,260'Delay chain burn-in for increased repeatability of physically unclonable functions'2012 8,108,739'High-speed testing of integrated devices'2012 7,971,164'Assessing resources required to complete a VLSI design'2011 7,924,633'Implementing boosted wordline voltage in memories'2011 7,911,827'Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels'2011 7,835,176'Implementing enhanced dual mode SRAM performance screen ring oscillator'2010 7,788,554'Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation'2010 7,782,691'Apparatus for guaranteed write through in domino read SRAM\'s'2010 7,768,851'Apparatus for implementing SRAM cell write performance evaluation'2010 7,737,757'Low power level shifting latch circuits with gated feedback for high speed integrated circuits'2010 7,724,585'Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability'2010 7,714,630'Method and apparatus to limit circuit delay dependence on voltage'2010 7,684,263'Method and circuit for implementing enhanced SRAM write and read performance ring oscillator'2010 7,609,542'Implementing enhanced SRAM read performance sort ring oscillator (PSRO)'2009 7,535,776'Circuit for improved SRAM write around with reduced read access penalty'2009 7,525,367'Method for implementing level shifter circuits for integrated circuits'2009 7,505,340'Method for implementing SRAM cell write performance evaluation'2009 7,502,276'Method and apparatus for multi-word write in domino read SRAMs'2009 7,480,170'Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2018Patents assigned to IBM (58)· patent assignee history

2009–2018Based in Rochester, MN, US· patent location history

2012–2016Patents assigned to HEBIG TRAVIS R (14)· patent assignee history

2012–2014Patents assigned to BEHRENDS DERICK G (9)· patent assignee history

2012–2014Patents assigned to CHRISTENSEN TODD A (9)· patent assignee history

2013–2014Patents assigned to LAUNSBACH MICHAEL (7)· patent assignee history

2015–2018Based in Lakeville, MN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	58	2009–2018
HEBIG TRAVIS Rself	14	2012–2016
BEHRENDS DERICK G	9	2012–2014
CHRISTENSEN TODD A	9	2012–2014
LAUNSBACH MICHAEL	7	2013–2014

Locations

Location	Patents	Span
Rochester, Minnesota, US	57	2009–2018
Lakeville, Minnesota, US	5	2015–2018