Inventor
Joshua M. Rubin
Inventor
Albany, NY, US
Overview
Patents· 67 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10DInorganic electric semiconductor devices25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10BElectronic memory devices5%
B82YSpecific uses or applications of nanostructures2%
H10NElectric solid-state devices not otherwise provided for2%
G11CStatic stores1%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application0%
G06NComputing arrangements based on specific computational models0%
PatentTitleYear
11,133,259Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network202111,114,410Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices202111,101,318Back-side memory element with local memory select transistor202111,094,637Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers202111,088,310Through-silicon-via fabrication in planar quantum devices202111,081,542Buried MIM capacitor structure with landing pads202111,081,424Micro-fluidic channels having various critical dimensions202111,069,679Reducing gate resistance in stacked vertical transport field effect transistors202110,833,081Forming isolated contacts in a stacked vertical transport field effect transistor (VTFET)202010,804,204Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate202010,770,460Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices202010,755,985Gate metal patterning for tight pitch applications202010,748,901Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices202010,727,139Three-dimensional monolithic vertical field effect transistor logic gates202010,714,420High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations202010,714,393Middle of the line subtractive self-aligned contacts202010,700,209Independent gate FinFET with backside gate contact202010,700,067Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices202010,692,768Vertical transport field-effect transistor architecture202010,679,890Nanosheet structure with isolated gate202010,636,791Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices202010,607,938Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices202010,608,080Bulk to silicon on insulator device202010,600,694Gate metal patterning for tight pitch applications202010,593,681Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple202010,580,738Direct bonded heterogeneous integration packaging structures202010,573,521Gate metal patterning to avoid gate stack attack due to excessive wet etching202010,546,918Multilayer buried metal-insultor-metal capacitor structures202010,546,915Buried MIM capacitor structure with landing pads202010,535,608Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate202010,483,344Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers201910,461,148Multilayer buried metal-insultor-metal capacitor structures201910,446,606Back-side memory element with local memory select transistor201910,373,874Middle of the line subtractive self-aligned contacts201910,332,959Bulk to silicon on insulator device201910,325,821Three-dimensional stacked vertical transport field effect transistor logic gate with buried power bus201910,283,411Stacked vertical transistor device for three-dimensional monolithic integration201910,243,043Self-aligned air gap spacer for nanosheet CMOS devices201910,229,915Mirror contact capacitor201910,217,674Three-dimensional monolithic vertical field effect transistor logic gates201910,211,341Tensile strained high percentage silicon germanium alloy FinFETS201910,199,352Wafer bonding edge protection using double patterning with edge exposure201910,192,888Metallized junction FinFET structures201910,147,815Fully silicided linerless middle-of-line (MOL) contact201810,128,377Independent gate FinFET with backside gate contact201810,121,877Vertical field effect transistor with metallic bottom region201810,103,065Gate metal patterning for tight pitch applications201810,032,674Middle of the line subtractive self-aligned contacts20189,997,607Mirrored contact CMOS with self-aligned source, drain, and back-gate20189,991,339Bulk to silicon on insulator device20189,978,871Bulk to silicon on insulator device20189,954,058Self-aligned air gap spacer for nanosheet CMOS devices20189,881,925'Mirror contact capacitor'20189,853,151Fully silicided linerless middle-of-line (MOL) contact20179,812,571'Tensile strained high percentage silicon germanium alloy FinFETs'20179,786,546'Bulk to silicon on insulator device'20179,761,498'Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs'20179,741,684'Wafer bonding edge protection using double patterning with edge exposure'20179,735,062'Defect reduction in channel silicon germanium on patterned silicon'20179,711,501'Interlayer via'20179,634,028'Metallized junction FinFET structures'20179,634,113'Fully silicided linerless middle-of-line (MOL) contact'20179,627,410'Metallized junction FinFET structures'20179,570,590'Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs'20179,472,621'CMOS structures with selective tensile strained NFET fins and relaxed PFET fins'20169,349,798'CMOS structures with selective tensile strained NFET fins and relaxed PFET fins'20168,080,839'Electro-mechanical transistor'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011Patents assigned to CHAE SOO-DOO (1)· patent assignee history
2011Patents assigned to KIM MOON-KYUNG (1)· patent assignee history
2011Patents assigned to LEE CHOONG-MAN (1)· patent assignee history
2011Based in Ithaca, NY, US· patent location history
2016–2021Patents assigned to IBM (65)· patent assignee history
2016–2021Based in Albany, NY, US· patent location history
2020Patents assigned to ELPIS TECH INC (1)· patent assignee history
2021Based in New Albany, OH, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 65 | 2016–2021 |
| CHAE SOO-DOO | 1 | 2011 |
| ELPIS TECH INC | 1 | 2020 |
| KIM MOON-KYUNG | 1 | 2011 |
| LEE CHOONG-MAN | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Albany, New York, US | 61 | 2016–2021 |
| New Albany, OH, US | 5 | 2021 |
| Ithaca, New York, US | 1 | 2011 |