Inventor
Nick Kepler
Inventor
Saratoga, CA, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
H10DInorganic electric semiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
PatentTitleYear
6,599,810'Shallow trench isolation formation with ion implantation'20036,514,844'Sidewall treatment for low dielectric constant (low K) materials by ion implantation'20036,380,040'Prevention of dopant out-diffusion during silicidation and junction formation'20026,380,047'Shallow trench isolation formation with two source/drain masks and simplified planarization mask'20026,274,511'Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer'20016,255,214'Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions'20016,239,031'Stepper alignment mark structure for maintaining alignment integrity'20016,238,986'Formation of junctions by diffusion from a doped film at silicidation'20016,204,177'Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal'20016,171,962'Shallow trench isolation formation without planarization mask'20016,169,005'Formation of junctions by diffusion from a doped amorphous silicon film during silicidation'20016,165,903'Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation'20006,162,699'Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery'20006,162,689'Multi-depth junction formation tailored to silicide formation'20006,156,615'Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions'20006,150,243'Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer'20006,143,624'Shallow trench isolation formation with spacer-assisted ion implantation'20006,130,467'Shallow trench isolation with spacers for improved gate oxide quality'20006,124,183'Shallow trench isolation formation with simplified reverse planarization mask'20006,100,145'Silicidation with silicon buffer layer and silicon spacers'20006,096,599'Formation of junctions by diffusion from a doped film into and through a silicide during silicidation'20006,090,712'Shallow trench isolation formation with no polish stop'20006,090,713'Shallow trench isolation formation with simplified reverse planarization mask'20006,074,927'Shallow trench isolation formation with trench wall spacer'20006,046,104'Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias'20006,037,671'Stepper alignment mark structure for maintaining alignment integrity'20006,030,862'Dual gate oxide formation with minimal channel dopant diffusion'20005,970,363'Shallow trench isolation formation with improved trench edge oxide'19995,970,362'Simplified shallow trench isolation formation with no polish stop'19995,930,645'Shallow trench isolation formation with reduced polish stop thickness'19995,795,820'Method for simplifying the manufacture of an interlayer dielectric stack'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2003Patents assigned to ADVANCED MICRO DEVICES INC (31)· patent assignee history
1998Based in San Jose, CA, US· patent location history
1999–2003Based in Saratoga, CA, US· patent location history
2003Based in Saragota, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 31 | 1998–2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 29 | 1999–2003 |
| Saragota, California, US | 1 | 2003 |
| San Jose, California, US | 1 | 1998 |