Inventor
Sean Shau-Tu Lu
Inventor
San Jose, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores22%
G06FElectric digital data processing17%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses11%
H03KPulse technique9%
B01LChemical or physical laboratory apparatus for general use4%
B41JTypewriters4%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
G06KGraphical data reading4%
B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering2%
C12QMeasuring or testing processes involving enzymes, nucleic acids or microorganisms2%
PatentTitleYear
10,953,397Diagnostic chip202110,940,693Logic circuitry202110,913,066Diagnostic chip202110,894,423Logic circuitry20219,818,471'Circuitry and methods for measuring and correcting duty-cycle distortion'20179,461,631'Circuitry and methods for measuring and correcting duty-cycle distortion'20169,330,218'Integrated circuits having input-output circuits with dedicated memory controller circuitry'20169,166,596'Memory interface circuitry with improved timing margins'20159,158,873'Circuit design technique for DQS enable/disable calibration'20159,059,716'Digital PVT compensation for delay chain'20158,922,264'Methods and apparatus for clock tree phase alignment'20148,816,743'Clock structure with calibration circuitry'20148,787,097'Circuit design technique for DQS enable/disable calibration'20148,680,905'Digital PVT compensation for delay chain'20148,565,034'Variation compensation circuitry for memory interface'20138,237,475'Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop'20127,800,257'Heat dissipater'20107,746,134'Digitally controlled delay-locked loops'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2017Patents assigned to ALTERA CORP (13)· patent assignee history
2010–2017Based in San Jose, CA, US· patent location history
2010Based in Westborough, MA, US· patent location history
2012–2014Patents assigned to CHONG YAN (4)· patent assignee history
2012–2014Patents assigned to HUANG JOSEPH (4)· patent assignee history
2012–2014Patents assigned to LU SEAN SHAU-TU (4)· patent assignee history
2021Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (4)· patent assignee history
2021Based in Corvallis, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 13 | 2010–2017 |
| CHONG YAN | 4 | 2012–2014 |
| HEWLETT PACKARD DEVELOPMENT CO | 4 | 2021 |
| HUANG JOSEPH | 4 | 2012–2014 |
| LU SEAN SHAU-TUself | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 13 | 2010–2017 |
| Corvallis, OR, US | 4 | 2021 |
| Westborough, Massachusetts, US | 1 | 2010 |