Inventor
Hazuki Okabayashi
Inventor
Osaka, JP
Overview
Patents· 10 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
9,170,841'Multiprocessor system for comparing execution order of tasks to a failure pattern'20157,970,998'Parallel caches operating in exclusive address ranges'20117,953,935'Cache memory system, and control method therefor'20117,594,099'Processor executing SIMD instructions'20097,555,610'Cache memory and control method thereof'20097,502,887'N-way set associative cache memory and control method thereof'20097,454,575'Cache memory and its controlling method'20087,380,112'Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags'20087,281,117'Processor executing SIMD instructions'20077,185,176'Processor executing SIMD instructions'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2008Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (4)· patent assignee history
2007–2009Based in Hirakata, JP· patent location history
2008–2011Based in Osaka, JP· patent location history
2009–2015Patents assigned to PANASONIC CORP (6)· patent assignee history
2015Patents assigned to PANASONIC IP MAN CO LTD (1)· patent assignee history
2015Based in Kyoto, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| PANASONIC CORP | 6 | 2009–2015 |
| MATSUSHITA ELECTRIC INDUSTRIAL CO LTD | 4 | 2007–2008 |
| PANASONIC IP MAN CO LTD | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Osaka, JP | 5 | 2008–2011 |
| Hirakata, JP | 4 | 2007–2009 |
| Kyoto, JP | 1 | 2015 |