Inventor

Geng Wang

Inventor

Stormville, NY, US

Overview

2002–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 186 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices29%

H10BElectronic memory devices17%

H01LSemiconductor devices16%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

G11CStatic stores2%

B82YSpecific uses or applications of nanostructures2%

G11BInformation storage based on relative movement between record carrier and transducer1%

LOC141%

A61KPreparations for medical, dental or toiletry purposes1%

PatentTitleYear

11,002,608Blackbody radiation source2021 10,921,192Plane source blackbody2021 10,883,882Method for making blackbody radiation source2021 10,818,668Metal trench capacitor and improved isolation and methods of manufacture2020 10,748,502Driving method of display panel and display device2020 10,679,998Vertical field effect transistor including integrated antifuse2020 10,680,000Vertical field effect transistor including integrated antifuse2020 10,629,142Liquid crystal display device2020 10,615,166Programmable device compatible with vertical transistor flow2020 10,615,159Integrated LDMOS and VFET transistors2020 10,586,800Anti-fuse with reduced programming voltage2020 10,553,354Method of manufacturing inductor with ferromagnetic cores2020 10,504,890High density nanosheet diodes2019 10,403,772Electrical and optical via connections on a same chip2019 10,396,169Nanosheet transistors having different gate dielectric thicknesses on the same chip2019 10,290,574Embedded metal-insulator-metal (MIM) decoupling capacitor in monolitic three-dimensional (3D) integrated circuit (IC) structure2019 10,269,790Forming horizontal bipolar junction transistor compatible with nanosheets2019 10,249,539Nanosheet transistors having different gate dielectric thicknesses on the same chip2019 10,249,709Stacked nanosheet field effect transistor device with substrate isolation2019 10,243,054Integrating standard-gate and extended-gate nanosheet transistors on the same substrate2019 10,236,381IFinFET2019 10,236,382Multiple finFET formation with epitaxy separation2019 10,229,919Vertical field effect transistor including integrated antifuse2019 10,229,920One-time programmable vertical field-effect transistor2019 10,224,329Forming gates with varying length using sidewall image transfer2019 10,224,334Anti-fuse with reduced programming voltage2019 10,157,935Nanosheet capacitor2018 10,141,403Integrating thin and thick gate dielectric nanosheet transistors on same chip2018 10,131,794Network copolymer crosslinked compositions and products comprising the same2018 10,090,293Integrated device with P-I-N diodes and vertical field effect transistors2018 10,079,280Asymmetric FET2018 10,032,909Vertical transistor having uniform bottom spacers2018 9,991,254Forming horizontal bipolar junction transistor compatible with nanosheets2018 9,935,014Nanosheet transistors having different gate dielectric thicknesses on the same chip2018 9,929,290'Electrical and optical via connections on a same chip'2018 9,917,090'Vertical antifuse structures'2018 9,898,177'Display processing method and portable mobile terminal'2018 9,899,391'Metal trench capacitor and improved isolation and methods of manufacture'2018 9,899,383'Forming gates with varying length using sidewall image transfer'2018 9,881,998'Stacked nanosheet field effect transistor device with substrate isolation'2018 9,859,373'Asymmetric FET'2018 9,852,982Anti-fuses with reduced programming voltages2017 9,847,246Multiple finFET formation with epitaxy separation2017 9,842,835'High density nanosheet diodes'2017 D0805091'Onboard vehicle device with graphical user interface'2017 9,806,084'Anti-fuse with reduced programming voltage'2017 9,799,647'Integrated device with P-I-N diodes and vertical field effect transistors'2017 9,793,270'Forming gates with varying length using sidewall image transfer'2017 9,768,166'Integrated LDMOS and VFET transistors'2017 D0795905'Onboard vehicle device with graphical user interface'2017 D0795904'Onboard vehicle device with graphical user interface'2017 D0795903'Onboard vehicle device with graphical user interface'2017 9,728,621'iFinFET'2017 9,653,480'Nanosheet capacitor'2017 9,627,511'Vertical transistor having uniform bottom spacers'2017 9,583,497'Metal trench capacitor and improved isolation and methods of manufacture'2017 9,557,290'Nanochannel electrode devices'2017 9,530,701'Method of forming semiconductor fins on SOI substrate'2016 9,507,485'Electronic device, displaying method and file saving method'2016 9,490,223'Structure to prevent deep trench moat charging and moat isolation fails'2016 9,484,269'Structure and method to control bottom corner threshold in an SOI device'2016 9,478,600'Method of forming substrate contact for semiconductor on insulator (SOI) substrate'2016 9,461,042'Sublithographic width finFET employing solid phase epitaxy'2016 9,406,569'Semiconductor device having diffusion barrier to reduce back channel leakage'2016 9,397,152'Multilayer MIM capacitor'2016 9,391,204'Asymmetric FET'2016 9,379,177'Deep trench capacitor'2016 9,343,320'Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench integration with fins'2016 9,293,520'Method of forming substrate contact for semiconductor on insulator (SOI) substrate'2016 9,287,272'Metal trench capacitor and improved isolation and methods of manufacture'2016 9,257,433'Structure and method of forming enhanced array device isolation for implanted plate EDRAM'2016 9,240,482'Asymmetric stressor DRAM'2016 9,238,041'Methods and compositions for regulating RNA import into mitochondria'2016 9,240,354'Semiconductor device having diffusion barrier to reduce back channel leakage'2016 9,228,994'Nanochannel electrode devices'2016 9,224,801'Multilayer MIM capacitor'2015 9,209,200'Methods for forming a self-aligned maskless junction butting for integrated circuits'2015 9,159,578'Self-aligned devices and methods of manufacture'2015 9,136,321'Low energy ion implantation of a junction butting region'2015 9,093,466'Epitaxial extension CMOS transistor'2015 9,087,928'High density memory cells using lateral epitaxy'2015 9,076,817'Epitaxial extension CMOS transistor'2015 9,064,745'Sublithographic width finFET employing solid phase epitaxy'2015 9,059,248'Junction butting on SOI by raised epitaxial structure and method'2015 9,059,213'Embedded DRAM for extremely thin semiconductor-on-insulator'2015 9,058,987'Rare-earth oxide isolated semiconductor fin'2015 9,059,320'Structure and method of forming enhanced array device isolation for implanted plate EDRAM'2015 9,054,126'Recessed single crystalline source and drain for semiconductor-on-insulator devices'2015 9,053,956'Trench capacitor with spacer-less fabrication process'2015 9,048,339'Deep trench capacitor'2015 9,029,862'Low resistance embedded strap for a trench capacitor'2015 8,962,423'Multilayer MIM capacitor'2015 8,937,345'Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact'2015 8,936,996'Structure and method for topography free SOI integration'2015 8,936,992'Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate'2015 8,921,198'Method and structure for forming a deep trench capacitor'2014 8,907,410'TSV structure with a built-in U-shaped FET transistor for improved characterization'2014 8,853,781'Rare-earth oxide isolated semiconductor fin'2014 8,846,470'Metal trench capacitor and improved isolation and methods of manufacture'2014 8,835,994'Reduced corner leakage in SOI structure and method'2014 8,836,050'Structure and method to fabricate a body contact'2014 8,829,585'High density memory cells using lateral epitaxy'2014 8,809,444'Network copolymer crosslinked emulsions and demulsifying compositions comprising the same'2014 8,809,994'Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate'2014 8,809,953'FET structures with trench implantation to improve back channel leakage and body resistance'2014 8,753,934'Structure and method to integrate embedded DRAM with FinFET'2014 8,754,461'Spacer isolation in deep trench'2014 8,742,503'Recessed single crystalline source and drain for semiconductor-on-insulator devices'2014 8,741,780'Reduced corner leakage in SOI structure and method'2014 8,723,243'Polysilicon/metal contact resistance in deep trench'2014 8,707,633'Field emergency shelter for fast minimally invasive cardiovascular surgery'2014 8,691,697'Self-aligned devices and methods of manufacture'2014 8,669,337'Network copolymer crosslinked compositions and methods of making the same'2014 8,647,945'Method of forming substrate contact for semiconductor on insulator (SOI) substrate'2014 8,642,423'Polysilicon/metal contact resistance in deep trench'2014 8,637,365'Spacer isolation in deep trench'2014 8,637,958'Structure and method for forming isolation and buried plate for trench capacitor'2014 8,629,017'Structure and method to form EDRAM on SOI substrate'2014 8,575,670'Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate'2013 8,564,069'Field effect transistors with low body resistance and self-balanced body potential'2013 8,536,649'Method to reduce threshold voltage variability with through gate well implant'2013 8,507,915'Low resistance embedded strap for a trench capacitor'2013 8,492,811'Self-aligned strap for embedded capacitor and replacement gate devices'2013 8,473,621'Method, system, and apparatus for creating content-on-demand service'2013 8,470,684'Suppression of diffusion in epitaxial buried plate for deep trenches'2013 8,455,327'Trench capacitor with spacer-less fabrication process'2013 8,455,979'Three dimensional integrated deep trench decoupling capacitors'2013 8,455,875'Embedded DRAM for extremely thin semiconductor-on-insulator'2013 8,421,139'Structure and method to integrate embedded DRAM with finfet'2013 8,409,989'Structure and method to fabricate a body contact'2013 8,395,217'Isolation in CMOSFET devices utilizing buried air bags'2013 8,372,721'Work function engineering for eDRAM MOSFETs'2013 8,354,675'Enhanced capacitance deep trench capacitor for EDRAM'2013 8,299,545'Method and structure to improve body effect and junction capacitance'2012 8,298,907'Structure and method of forming enhanced array device isolation for implanted plate eDRAM'2012 8,299,573'Trench capacitor'2012 8,298,884'Method to reduce threshold voltage variability with through gate well implant'2012 8,298,908'Structure and method for forming isolation and buried plate for trench capacitor'2012 8,299,530'Structure and method to fabricate pFETS with superior GIDL by localizing workfunction'2012 8,273,629'Through-gate implant for body dopant'2012 8,242,549'Dynamic random access memory cell including an asymmetric transistor and a columnar capacitor'2012 8,236,632'FET structures with trench implantation to improve back channel leakage and body resistance'2012 8,232,162'Forming implanted plates for high aspect ratio trenches using staged sacrificial layer removal'2012 8,227,310'Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact and methods of making'2012 8,222,104'Three dimensional integrated deep trench decoupling capacitors'2012 8,222,154'Fin and finFET formation by angled ion implantation'2012 8,188,528'Structure and method to form EDRAM on SOI substrate'2012 8,168,507'Structure and method of forming enhanced array device isolation for implanted plate EDRAM'2012 8,133,781'Method of forming a buried plate by ion implantation'2012 8,129,797'Work function engineering for eDRAM MOSFETs'2012 7,923,815'DRAM having deep trench capacitors with lightly doped buried plates'2011 7,863,646'Dual oxide stress liner'2011 7,791,124'SOI deep trench capacitor employing a non-conformal inner spacer'2010 7,790,530'Dual port gain cell with side and top gated read transistor'2010 7,785,959'Method of multi-port memory fabrication with parallel connected trench capacitors in a cell'2010 7,776,706'Forming SOI trench memory with single-sided buried strap'2010 7,732,872'Integration scheme for multiple metal gate work function structures'2010 7,723,201'Structure and method for making on-chip capacitors with various capacitances'2010 7,668,003'Dynamic random access memory circuit, design structure and method'2010 7,596,038'Floating body control in SOI DRAM'2009 7,550,359'Methods involving silicon-on-insulator trench memory with implanted plate'2009 7,485,525'Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell'2009 7,459,743'Dual port gain cell with side and top gated read transistor'2008 7,445,987'Offset vertical device'2008 7,445,988'Trench memory'2008 7,439,149'Structure and method for forming SOI trench memory with single-sided strap'2008 7,440,353'Floating body control in SOI DRAM'2008 7,408,229'Structure and method for accurate deep trench resistance measurement'2008 7,388,261'Structure and method for accurate deep trench resistance measurement'2008 7,384,842'Methods involving silicon-on-insulator trench memory with implanted plate'2008 7,354,822'Method of forming a MOSFET with dual work function materials'2008 7,326,986'Trench memory'2008 7,319,259'Structure and method for accurate deep trench resistance measurement'2008 7,294,879'Vertical MOSFET with dual work function materials'2007 7,271,973'Flying height compensation for up/down bit error rate trend difference'2007 7,262,451'High performance embedded DRAM technology with strained silicon'2007 7,247,905'Offset vertical device'2007 7,212,000'Detection of a defective disk of a hard disk drive'2007 7,102,914'Gate controlled floating well vertical MOSFET'2006 7,089,649'Method of estimating a thermal pole tip protrusion for a head gimbal assembly'2006 7,045,873'Dynamic threshold voltage MOSFET on SOI'2006 6,972,461'Channel MOSFET with strained silicon channel on strained SiGe'2005 6,930,004'Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling'2005 6,912,098'Method for dynamically measuring suspension in-plane and out-plane thermal drift hard disk drives'2005 6,791,775'Method and apparatus to distinguish effects of adjacent track encroachment from head thermal movement'2004 6,489,762'Method to detect junction induced signal instability from GMR/MR heads'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2007Based in San Jose, CA, US· patent location history

2005–2020Patents assigned to IBM (147)· patent assignee history

2005–2020Based in Stormville, NY, US· patent location history

2012–2018Patents assigned to WANG GENG (63)· patent assignee history

2012–2016Patents assigned to PEI CHENGWEN (37)· patent assignee history

2012–2015Patents assigned to CHENG KANGGUO (29)· patent assignee history

2012–2016Patents assigned to ERVIN JOSEPH (26)· patent assignee history

2012–2014Based in Hopewell Junction, NY, US· patent location history

2014–2017Based in Shenyang, CN· patent location history

2016–2021Based in Beijing, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	147	2005–2020
WANG GENGself	63	2012–2018
PEI CHENGWEN	37	2012–2016
CHENG KANGGUO	29	2012–2015
ERVIN JOSEPH	26	2012–2016

Locations

Location	Patents	Span
Stormville, New York, US	147	2005–2020
Hopewell Junction, New York, US	12	2012–2014
San Jose, California, US	6	2002–2007
Beijing, CN	5	2016–2021
Shenyang, CN	5	2014–2017