Inventor
JAVIER A. DELACRUZ
Inventor
US
Overview
Patents· 70 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10DInorganic electric semiconductor devices6%
G06FElectric digital data processing4%
H10BElectronic memory devices3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H05KPrinted circuits3%
G01RMeasuring electric variables2%
G11CStatic stores2%
PatentTitleYear
12,564,084Bonded structures without intervening adhesive202612,557,659Wire bonding method and apparatus for electromagnetic interference shielding202612,500,209Embedded organic interposer for high bandwidth202512,451,439Bonded structure including an obstructive element directly bonded to a semiconductor element without an adhesive202512,451,445Protective elements for bonded structures202512,431,449Circuitry for electrical redundancy in bonded structures202512,362,182Direct-bonded native interconnects and active base die202512,308,332Circuitry for electrical redundancy in bonded structures202512,293,9933D chip sharing data bus202512,293,1083D memory circuit202512,288,771Apparatus for non-volatile random access memory stacks202512,283,572Symbiotic network on layers202512,278,215Integrated voltage regulator and passive components202512,271,032Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects202512,272,730Transistor level interconnection methodologies utilizing 3D interconnects202512,255,176Scalable architecture for reduced cycles across SOC202512,218,059Stacked IC structure with orthogonal interconnect layers202512,176,303Wafer-level bonding of obstructive elements202412,174,246Security circuitry for bonded structures202412,154,858Connecting multiple chips using an interconnect device202412,142,5283D chip with shared clock distribution network202412,113,054Non-volatile dynamic random access memory202412,100,684Bonded structures202412,094,835Wire bonding method and apparatus for electromagnetic interference shielding202412,080,672Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive202412,074,092Hard IP blocks with physically bidirectional passageways202412,057,383Bonded structures with integrated passive component202411,967,575Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes202411,929,347Mixed exposure for large die202411,916,076Device disaggregation for improved performance202411,901,281Bonded structures with integrated passive component202411,894,345Integrated voltage regulator and passive components202411,881,454Stacked IC structure with orthogonal interconnect layers202411,876,076Apparatus for non-volatile random access memory stacks202411,862,604Systems and methods for releveled bump planes for chiplets202411,860,415Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects202411,862,602Scalable architecture for reduced cycles across SOC202411,848,284Protective elements for bonded structures202311,837,556Wire bonding method and apparatus for electromagnetic interference shielding202311,830,804Over and under interconnects202311,824,0423D chip sharing data bus202311,824,046Symbiotic network on layers202311,823,906Direct-bonded native interconnects and active base die202311,817,409Directly bonded structures without intervening adhesive and methods for forming the same202311,804,469Active bridging apparatus202311,728,287Wafer-level bonding of obstructive elements202311,721,653Circuitry for electrical redundancy in bonded structures202311,688,776Transistor level interconnection methodologies utilizing 3D interconnects202311,670,615Bonded structures202311,626,363Bonded structures with integrated passive component202311,610,846Protective elements for bonded structures including an obstructive element202311,599,2993D memory circuit202311,600,542Cavity packages202311,515,291Integrated voltage regulator and passive components202211,476,213Bonded structures without intervening adhesive202211,469,214Stacked architecture for three-dimensional NAND202211,385,278Security circuitry for bonded structures202211,373,963Protective elements for bonded structures202211,369,020Stacked transmission line202211,355,443Dielets on flexible and stretchable packaging for microelectronics202211,348,898Systems and methods for releveled bump planes for chiplets202211,335,647Wire bonding method and apparatus for electromagnetic interference shielding202211,296,044Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes202211,289,333Direct-bonded native interconnects and active base die202211,270,979Symbiotic network on layers202211,264,361Network on layer enabled architectures202211,264,357Mixed exposure for large die202211,205,625Wafer-level bonding of obstructive elements202111,157,670Systems and methods for inter-die block level design202111,139,283Abstracted NAND logic in stacks2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2023Patents assigned to XCELSIS CORP (7)· patent assignee history
2021–2026Based in US· patent location history
2022–2025Patents assigned to ADEIA SEMICONDUCTOR INC (15)· patent assignee history
2022–2024Patents assigned to INVENSAS LLC (7)· patent assignee history
2023–2026Patents assigned to ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC (22)· patent assignee history
2023–2026Patents assigned to ADEIA SEMICONDUCTOR TECH LLC (14)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC | 22 | 2023–2026 |
| ADEIA SEMICONDUCTOR INC | 15 | 2022–2025 |
| ADEIA SEMICONDUCTOR TECH LLC | 14 | 2023–2026 |
| INVENSAS LLC | 7 | 2022–2024 |
| XCELSIS CORP | 7 | 2021–2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 70 | 2021–2026 |