Inventor

Donald M. Kenney

Inventor

Shelburne, VT, US

Overview

1981–2000

Patent span

Electricity

Primary field (CPC H)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices32%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests21%

H10DInorganic electric semiconductor devices17%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

G11CStatic stores5%

B82YSpecific uses or applications of nanostructures1%

C23CCoating metallic material1%

H01JElectric discharge tubes or discharge lamps1%

H03KPulse technique1%

PatentTitleYear

6,139,647'Selective removal of vertical portions of a film'2000 6,020,250'Stacked devices'2000 5,930,640'Mechanical supports for very thin stacked capacitor plates'1999 5,885,425'Method for selective material deposition on one side of raised or recessed features'1999 5,801,089'Method of forming stacked devices'1998 5,767,017'Selective removal of vertical portions of a film'1998 5,744,386'Method of fabricating a memory cell in a substrate trench'1998 5,719,080'Semiconductor trench capacitor cell having a buried strap'1998 5,710,057'SOI fabrication method'1998 5,691,549'Sidewall strap'1997 5,684,314'Trench capacitor precharge structure and leakage shield'1997 5,684,313'Vertical precharge structure for DRAM'1997 5,672,537'Method for preparing a narrow angle defined trench in a substrate'1997 5,656,544'Process for forming a polysilicon electrode in a trench'1997 5,641,694'Method of fabricating vertical epitaxial SOI transistor'1997 5,640,030'Double dense ferroelectric capacitor cell memory'1997 5,635,419'Porous silicon trench and capacitor structures'1997 5,610,441'Angle defined trench conductor for a semiconductor device'1997 5,583,368'Stacked devices'1996 5,576,566'Semiconductor trench capacitor cell having a buried strap'1996 5,532,965'Memory precharge scheme using spare column'1996 5,521,118'Sidewall strap'1996 5,508,542'Porous silicon trench and capacitor structures'1996 5,466,636'Method of forming borderless contacts using a removable mandrel'1995 5,414,656'Low charge consumption memory'1995 5,412,246'Low temperature plasma oxidation process'1995 5,399,516'Method of making shadow RAM cell having a shallow trench EEPROM'1995 5,384,281'Non-conformal and oxidizable etch stops for submicron features'1995 5,365,097'Vertical epitaxial SOI transistor, memory cell and fabrication methods'1994 5,360,758'Self-aligned buried strap for trench type DRAM cells'1994 5,348,905'Method of making diffused buried plate trench DRAM cell array'1994 5,330,935'Low temperature plasma oxidation process'1994 5,264,716'Diffused buried plate trench dram cell array'1993 5,254,503'Process of making and using micro mask'1993 5,196,722'Shadow ram cell having a shallow trench eeprom'1993 RE033972'Two square memory cells'1992 5,001,525'Two square memory cells having highly conductive word lines'1991 4,970,689'Charge amplifying trench memory cell'1990 4,939,567'Trench interconnect for CMOS diffusion regions'1990 4,914,740'Charge amplifying trench memory cell'1990 4,838,991'Process for defining organic sidewall structures'1989 4,833,094'Method of making a dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes'1989 4,801,988'Semiconductor trench capacitor cell with merged isolation and node trench construction'1989 4,785,337'Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes'1988 4,769,786'Two square memory cells'1988 4,751,558'High density memory with field shield'1988 4,648,073'Sequential shared access lines memory cells'1987 4,642,491'Single transistor driver circuit'1987 4,511,911'Dense dynamic memory cell structure and process'1985 4,470,191'Process for making complementary transistors by sequential implantations using oxidation barrier masking layer'1984 4,364,074'V-MOS Device with self-aligned multiple electrodes'1982 4,326,332'Method of making a high density V-MOS memory array'1982 4,295,924'Method for providing self-aligned conductor in a V-groove device'1981

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1981–2000Patents assigned to IBM (47)· patent assignee history

1981–2000Based in Shelburne, VT, US· patent location history

1984–1998Based in Shelbourne, VT, US· patent location history

1997Based in Chittenden County, VT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	47	1981–2000

Locations

Location	Patents	Span
Shelburne, VT, US	49	1981–2000
Shelbourne, VT, US	2	1984–1998
Chittenden County, VT, US	2	1997