Inventor

Shoji Ariizumi

Inventor

Tokyo, JP

Overview

28→

Patents

1981–1992

Patent span

Electricity

Primary field (CPC H)

Patents· 28 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices22%

G11CStatic stores18%

H10DInorganic electric semiconductor devices18%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%

H03KPulse technique7%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

G05FSystems for regulating electric or magnetic variables3%

H02HEmergency protective circuit arrangements1%

PatentTitleYear

5,101,262'Semiconductor memory device and method of manufacturing it'1992 4,907,057'Semiconductor device'1990 4,893,159'Protected MOS transistor circuit'1990 4,892,841'Method of manufacturing a read only semiconductor memory device'1990 4,855,248'Method of making a semiconductor ROM device'1989 4,760,560'Random access memory with resistance to crystal lattice memory errors'1988 4,755,864'Semiconductor read only memory device with selectively present mask layer'1988 4,748,492'Read only memory'1988 4,737,835'Read only memory semiconductor device'1988 4,725,746'MOSFET buffer circuit with an improved bootstrapping circuit'1988 4,673,969'Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device'1987 4,649,412'Read only semiconductor memory device with polysilicon drain extensions'1987 4,648,075'Redundancy circuit for a semiconductor memory device'1987 4,578,694'Inverter circuit provided with gate protection'1986 4,571,706'Semiconductor memory device'1986 4,554,469'Static bootstrap semiconductor drive circuit'1985 4,549,102'Driver circuit having a bootstrap buffer circuit'1985 4,544,941'Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device'1985 4,541,006'Static memory having load polysilicon resistors formed over driver FET drains'1985 4,539,490'Charge pump substrate bias with antiparasitic guard ring'1985 4,535,426'Semiconductor memory device'1985 4,527,213'Semiconductor integrated circuit device with circuits for protecting an input section against an external surge'1985 4,504,746'Semiconductor buffer circuit using enhancement-mode, depletion-mode and zero threshold mode transistors'1985 4,453,175'MOS Static RAM layout with polysilicon resistors over FET gates'1984 4,413,403'Method of producing semiconductor devices'1983 4,399,520'Semiconductor integrated circuit device'1983 4,384,220'MOS Transistor circuit with a power-down function'1983 4,247,918'Electrically alterable nonvolatile memory'1981

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1981–1990Patents assigned to TOKYO SHIBAURA ELECTRIC CO (17)· patent assignee history

1981–1992Based in Tokyo, JP· patent location history

1987–1992Patents assigned to TOSHIBA KK (11)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TOKYO SHIBAURA ELECTRIC CO	17	1981–1990
TOSHIBA KK	11	1987–1992

Locations

Location	Patents	Span
Tokyo, JP	28	1981–1992