Inventor
Siu Lung Chan
Inventor
San Jose, CA, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
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PatentTitleYear
9,576,673'Sensing multiple reference levels in non-volatile storage elements'20179,047,954'Bit line resistance compensation'20158,908,432'Bit line resistance compensation'20148,902,659'Shared-bit-line bit line setup scheme'20148,873,303'Non-volatile memory and method with shared processing for an aggregate of read/write circuits'20148,743,618'Bit line resistance compensation'20148,705,293'Compact sense amplifier for non-volatile memory suitable for quick pass write'20148,630,120'Compact sense amplifier for non-volatile memory'20148,542,529'Non-volatile memory and method with power-saving read and program-verify operations'20138,228,741'Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits'20128,154,923'Non-volatile memory and method with power-saving read and program-verify operations'20127,957,185'Non-volatile memory and method with power-saving read and program-verify operations'20117,894,273'Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits'20117,817,476'Non-volatile memory and method with shared processing for an aggregate of read/write circuits'20107,768,836'Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits'20107,609,556'Non-volatile memory with improved program-verify operations'20097,593,277'Method for compensated sensing in non-volatile memory'20097,570,513'Non-volatile memory and method with power-saving read and program-verify operations'20097,499,324'Non-volatile memory and method with control gate compensation for source line bias errors'20097,471,575'Non-volatile memory and method with shared processing for an aggregate of read/write circuits'20087,447,081'Methods for improved program-verify operations in non-volatile memories'20087,391,645'Non-volatile memory and method with compensation for source line bias errors'20087,391,646'Non-volatile memory and method with control gate compensation for source line bias errors'20087,327,619'Reference sense amplifier for non-volatile memory'20087,324,393'Method for compensated sensing in non-volatile memory'20087,310,255'Non-volatile memory with improved program-verify operations'20077,286,406'Method for controlled programming of non-volatile memory exhibiting bit line coupling'20077,251,160'Non-volatile memory and method with power-saving read and program-verify operations'20077,224,614'Methods for improved program-verify operations in non-volatile memories'20077,206,235'Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling'20077,173,854'Non-volatile memory and method with compensation for source line bias errors'20077,170,784'Non-volatile memory and method with control gate compensation for source line bias errors'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2013Patents assigned to SANDISK CORP (22)· patent assignee history
2007–2015Based in San Jose, CA, US· patent location history
2012–2015Patents assigned to SANDISK TECHNOLOGIES INC (9)· patent assignee history
2012–2014Patents assigned to CHAN SIU LUNG (7)· patent assignee history
2012–2014Patents assigned to LI YAN (6)· patent assignee history
2014Patents assigned to KIM KWANG-HO (2)· patent assignee history
2017Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK CORP | 22 | 2007–2013 |
| SANDISK TECHNOLOGIES INC | 9 | 2012–2015 |
| CHAN SIU LUNGself | 7 | 2012–2014 |
| LI YAN | 6 | 2012–2014 |
| KIM KWANG-HO | 2 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 31 | 2007–2015 |
| Santa Clara, California, US | 1 | 2017 |