Inventor

Jorge A. Kittl

Inventor

Round Rock, TX, US

Overview

1999–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 63 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices31%

H01LSemiconductor devices23%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

G11CStatic stores6%

G06NComputing arrangements based on specific computational models4%

H10BElectronic memory devices4%

H10NElectric solid-state devices not otherwise provided for2%

G06FElectric digital data processing2%

C23CCoating metallic material1%

PatentTitleYear

11,101,320System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)2021 10,909,449Monolithic multi-bit weight cell for neuromorphic computing2021 10,878,317Method and system for performing analog complex vector-matrix multiplication2020 10,872,6622T2R binary weight cell with high on/off ratio background2020 10,832,774Variation resistant 3T3R binary weight cell with low output current and high on/off ratio2020 10,790,002Giant spin hall-based compact neuromorphic cell optimized for differential read inference2020 10,763,207Interconnects having long grains and methods of manufacturing the same2020 10,739,186Bi-directional weight cell2020 10,679,688Ferroelectric-based memory cell usable in on-logic chip memory2020 10,614,868Memory device with strong polarization coupling2020 10,510,665Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same2019 10,510,886Method of providing reacted metal source-drain stressors for tensile channel stress2019 10,461,751FE-FET-based XNOR cell usable in neuromorphic computing2019 10,297,673Methods of forming semiconductor devices including conductive contacts on source/drains2019 10,283,638Structure and method to achieve large strain in NS without addition of stack-generated defects2019 10,205,025Methods to achieve strained channel finFET devices2019 10,170,549Strained stacked nanosheet FETs and/or quantum well stacked nanosheet2019 10,147,793FinFET devices including recessed source/drain regions having optimized depths2018 9,978,833Methods for varied strain on nano-scale field effect transistor devices2018 9,966,449Methods of forming semiconductor devices, including forming a contact including an alkaline earth metal on a semiconductor layer, and related devices2018 9,941,405Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same2018 9,917,158'Device contact structures including heterojunctions for low contact resistance'2018 9,893,187'Sacrificial non-epitaxial gate stressors'2018 9,871,139'Sacrificial epitaxial gate stressors'2018 9,847,245Filling processes2017 9,831,323Structure and method to achieve compressively strained Si NS2017 9,773,886'Nanosheet and nanowire devices having doped internal spacers and methods of manufacturing the same'2017 9,768,062'Method for forming low parasitic capacitance source and drain contacts'2017 9,698,234'Interface layer for gate stack using O3 post treatment'2017 9,685,509'Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions'2017 9,653,287'S/D connection to individual channel layers in a nanosheet FET'2017 9,634,140'Fabricating metal source-drain stressor in a MOS device channel'2017 9,614,002'0T bi-directional memory cell'2017 9,613,907'Low resistivity damascene interconnect'2017 9,601,586'Methods of forming semiconductor devices, including forming a metal layer on source/drain regions'2017 9,525,053'Integrated circuit devices including strained channel regions and methods of forming the same'2016 9,484,423'Crystalline multiple-nanosheet III-V channel FETs'2016 9,431,492'Integrated circuit devices including contacts and methods of forming the same'2016 9,431,529'Confined semi-metal field effect transistor'2016 9,406,508'Methods of forming a semiconductor layer including germanium with low defectivity'2016 9,343,298'Metal-insulator-metal capacitor and method for manufacturing thereof'2016 9,177,812'Method of manufacturing low resistivity contacts on n-type germanium'2015 8,649,154'Method for producing a metal-insulator-metal capacitor for use in semiconductor devices'2014 8,405,166'Dielectric layer for flash memory device and method for manufacturing thereof'2013 8,372,750'Method and system for improved nickel silicide'2013 8,344,460'Method for forming a nickelsilicide FUSI gate'2013 8,183,137'Use of dopants to provide low defect gate full silicidation'2012 7,989,344'Method for forming a nickelsilicide FUSI gate'2011 7,851,297'Dual workfunction semiconductor device'2010 7,825,025'Method and system for improved nickel silicide'2010 7,759,748'Semiconductor device with reduced diffusion of workfunction modulating element'2010 7,504,329'Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET'2009 7,491,635'Method for forming a fully silicided gate and devices obtained thereof'2009 6,777,300'Method to improve silicide formation on polysilicon'2004 6,429,455'Method to enhance the formation of nucleation sites on silicon structures and an improved silicon structure'2002 6,372,566'Method of forming a silicide layer using metallic impurities and pre-amorphization'2002 6,326,289'Method of forming a silicide layer using a pre-amorphization implant which is blocked from source/drain regions by a layer of photoresist'2001 6,242,333'Method to enhance the formation of nucleation sites on silicon structures and an improved silicon structure'2001 6,204,132'Method of forming a silicide layer using an angled pre-amorphization implant'2001 6,187,656'CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes'2001 6,048,784'Transistor having an improved salicided gate and method of construction'2000 6,046,105'Preferential lateral silicidation of gate with low source and drain silicon consumption'2000 6,004,871'Implant enhancement of titanium silicidation'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2013Patents assigned to TEXAS INSTRUMENTS INC (15)· patent assignee history

1999–2004Based in Plano, TX, US· patent location history

2009–2013Based in Waterloo, BE· patent location history

2010–2016Patents assigned to IMEC (8)· patent assignee history

2013–2019Patents assigned to KITTL JORGE A (5)· patent assignee history

2013–2016Patents assigned to KITTL JORGE (4)· patent assignee history

2013–2016Based in Hamme-Mille, BE· patent location history

2016–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (40)· patent assignee history

2016–2019Based in Round Rock, TX, US· patent location history

2017–2021Based in Austin, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SAMSUNG ELECTRONICS CO LTD	40	2016–2021
TEXAS INSTRUMENTS INC	15	1999–2013
IMEC	8	2010–2016
KITTL JORGE Aself	5	2013–2019
KITTL JORGEself	4	2013–2016

Locations

Location	Patents	Span
Round Rock, Texas, US	24	2016–2019
Austin, Texas, US	13	2017–2021
Plano, Texas, US	10	1999–2004
Waterloo, BE	9	2009–2013
Hamme-Mille, BE	4	2013–2016