LexDanaLexDanabeta
Inventor

Jun Lu

Inventor
San Jose, CA, US

Overview

99→
Patents
2009–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 99 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1041%
H01LSemiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10DInorganic electric semiconductor devices8%
H01FMagnets3%
H02JElectric power networks3%
Y10TTechnical subjects covered by former us classification3%
H05KPrinted circuits1%
G06FElectric digital data processing1%
H02PControl or regulation of electric motors, electric generators or dynamo-electric converters1%
PatentTitleYear
10,721,684Electronic device having two processors to process data202010,600,727Molded intelligent power module for motors202010,504,823Power semiconductor device with small contact footprint and the preparation method201910,396,019Molded intelligent power module and method of making the same201910,177,080Molded intelligent power module201910,141,249Molded intelligent power module and method of making the same201810,043,736Hybrid packaged lead frame based multi-chip semiconductor device with multiple interconnecting structures20189,929,076'Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided multiple connecting areas for connection to the flipped MOSFET electrodes'20189,854,686Preparation method of a thin power device20179,786,583'Power semiconductor package device having locking mechanism, and preparation method thereof'20179,768,146'Battery protection package and process of making the same'20179,735,094'Combined packaged power semiconductor device'20179,685,430'Embedded package and method thereof'20179,679,833'Semiconductor package with small gate clip and assembly method'20179,653,383'Semiconductor device with thick bottom metal and preparation method thereof'20179,653,424'Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method'20179,646,920'Power semiconductor device with small contact footprint and the preparation method'20179,564,406'Battery protection package and process of making the same'20179,520,380'Wafer process for molded chip scale package (MCSP) with thick backside metallization'20169,472,491'Semiconductor package with small gate clip and assembly method'20169,437,528'Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof'20169,437,587'Flip chip semiconductor device'20169,437,530'Combined packaged power semiconductor device'20169,431,328'Power device and preparation method thereof'20169,425,181'Method of hybrid packaging a lead frame based multi-chip semiconductor device with multiple interconnecting structures'20169,412,684'Top exposed semiconductor chip package'20169,397,029'Power semiconductor package device having locking mechanism, and preparation method thereof'20169,391,005'Method for packaging a power device with bottom source electrode'20169,337,131'Power semiconductor device and the preparation method'20169,318,424'MCSP power semiconductor devices and preparation methods thereof'20169,318,603'Method of making a low-Rdson vertical power MOSFET device'20169,305,870'Power semiconductor device and preparation method thereof'20169,293,397'Power device and preparation method thereof'20169,281,265'Packaging structure of a semiconductor device'20169,269,699'Embedded package and method thereof'20169,245,861'Wafer process for molded chip scale package (MCSP) with thick backside metallization'20169,230,949'Method of making stacked multi-chip packaging structure'20169,214,419'Power semiconductor device and preparation method thereof'20159,214,417'Combined packaged power semiconductor device'20159,184,117'Stacked dual-chip packaging structure and preparation method thereof'20159,171,788'Semiconductor package with small gate clip and assembly method'20159,165,866'Stacked dual chip package having leveling projections'20159,147,586'Semiconductor package with connecting plate for internal connection'20159,087,828'Semiconductor device with thick bottom metal and preparation method thereof'20159,054,091'Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures'20159,040,357'Semiconductor packaging method using connecting plate for internal connection'20159,041,172'Semiconductor device for restraining creep-age phenomenon and fabricating method thereof'20159,006,870'Stacked multi-chip packaging structure and manufacturing method thereof'20159,006,901'Thin power device and preparation method thereof'20158,952,509'Stacked multi-chip bottom source semiconductor device and preparation method thereof'20158,933,518'Stacked power semiconductor device using dual lead frame'20158,933,549'Dual-leadframe multi-chip package'20158,933,550'Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors'20158,865,523'Semiconductor package and fabrication method thereof'20148,815,649'Multi-layer lead frame package and method of fabrication'20148,778,735'Packaging method of molded wafer level chip scale package (WLCSP)'20148,722,466'Semiconductor packaging and fabrication method using connecting plate for internal connection'20148,722,468'Semiconductor encapsulation method'20148,709,893'Method of making a low-Rdson vertical power MOSFET device'20148,709,867'Dual-leadframe multi-chip package and method of manufacture'20148,703,545'Aluminum alloy lead-frame and its use in fabrication of power semiconductor package'20148,686,546'Combined packaged power semiconductor device'20148,669,650'Flip chip semiconductor device'20148,642,385'Wafer level package structure and the fabrication method thereof'20148,586,414'Top exposed package and assembly method'20138,581,376'Stacked dual chip package and method of fabrication'20138,575,006'Process to form semiconductor packages with external leads'20138,563,361'Packaging method of molded wafer level chip scale package (WLCSP)'20138,563,417'Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process'20138,563,360'Power semiconductor device package and fabrication method'20138,564,110'Power device with bottom source electrode'20138,519,525'Semiconductor encapsulation and method thereof'20138,513,784'Multi-layer lead frame package and method of fabrication'20138,481,368'Semiconductor package of a flipped MOSFET and its manufacturing method'20138,482,048'Metal oxide semiconductor field effect transistor integrating a capacitor'20138,476,752'Package structure for DC-DC converter'20138,455,303'Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method'20138,436,429'Stacked power semiconductor device using dual lead frame and manufacturing method'20138,431,993'Semiconductor package for forming a leadframe package'20138,344,519'Stacked-die package for battery power management'20138,302,287'Method of manufacturing a multilayer inductor'20128,283,212'Method of making a copper wire bond package'20128,247,288'Method of integrating a MOSFET with a capacitor'20128,222,088'Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method'20128,217,503'Package structure for DC-DC converter'20128,178,954'Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors'20128,154,108'Dual-leadframe multi-chip package and method of manufacture'20128,076,183'Method of attaching an interconnection plate to a semiconductor die within a leadframe package'20118,058,961'Lead frame-based discrete power inductor'20118,049,315'Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package'20117,971,340'Planar grooved power inductor structure and method'20117,948,346'Planar grooved power inductor structure and method'20117,939,370'Power semiconductor package'20117,898,092'Stacked-die package for battery power management'20117,884,696'Lead frame-based discrete power inductor'20117,884,454'Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package'20117,843,303'Multilayer inductor'20107,729,690'Backup and restore of user data for mobile telephone'20107,502,390'Optimized interleaver and/or deinterleaver design'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2020Based in San Jose, CA, US· patent location history
2010–2018Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (86)· patent assignee history
2010Based in Nanjing, CN· patent location history
2011–2018Patents assigned to LU JUN (47)· patent assignee history
2011–2018Patents assigned to XUE YAN XUN (34)· patent assignee history
2012–2018Patents assigned to YILMAZ HAMZA (22)· patent assignee history
2012–2016Patents assigned to HO YUEH-SE (20)· patent assignee history
2020Based in Shanghai, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALPHA & OMEGA SEMICONDUCTOR862010–2018
LU JUNself472011–2018
XUE YAN XUN342011–2018
YILMAZ HAMZA222012–2018
HO YUEH-SE202012–2016
Locations
LocationPatentsSpan
San Jose, California, US972009–2020
Shanghai, CN12020
Nanjing, CN12010