Inventor

Peter W. Lee

Inventor

Saratoga, CA, US

Overview

1986–2020

Patent span

Physics

Primary field (CPC G)

Patents· 191 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores47%

H10BElectronic memory devices23%

H10DInorganic electric semiconductor devices7%

H01LSemiconductor devices4%

G06FElectric digital data processing3%

H10NElectric solid-state devices not otherwise provided for3%

Y10TTechnical subjects covered by former us classification2%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

F16CShafts1%

PatentTitleYear

10,600,793Fabricating memory devices with optimized gate oxide thickness2020 10,319,727Fabricating memory devices with optimized gate oxide thickness2019 10,037,290Dual-port memories and input/output circuits for preventing failures corresponding to concurrent accesses of dual-port memory cells2018 10,037,400Integrated circuit manufacturing process for aligning threshold voltages of transistors2018 9,830,976Systems and methods for a high performance memory cell structure2017 9,666,286'Self-timed SLC NAND pipeline and concurrent program without verification'2017 9,659,636'NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations'2017 9,613,704'2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify'2017 9,595,319'Partial/full array/block erase for 2D/3D hierarchical NAND'2017 9,558,811'Disturb-proof static RAM cells'2017 9,530,492'NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations'2016 9,524,773'Multi-task concurrent/pipeline NAND operations on all planes'2016 9,490,427'Resistive random access memory cell structure'2016 9,443,578'NAND array architecture for multiple simultaneous program and read'2016 9,443,579'VSL-based VT-compensation and analog program scheme for NAND array without CSL'2016 9,437,306'NAND array architecture for multiple simutaneous program and read'2016 9,424,911'Method and apparatus for screening memory cells for disturb failures'2016 9,324,417'Systems and methods for avoiding read disturbance in a static random-access memory (SRAM)'2016 9,293,205'Multi-task concurrent/pipeline NAND operations on all planes'2016 9,275,731'Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)'2016 9,263,137'NAND array architecture for multiple simutaneous program and read'2016 9,245,961'Reducing source contact to gate spacing to decrease transistor pitch'2016 9,230,677'NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operations'2016 9,214,230'Resistive random access memory cell structure with reduced programming voltage'2015 9,183,940'Low disturbance, power-consumption, and latency in NAND read and program-verify operations'2015 9,177,645'10T NVSRAM cell and cell operations'2015 9,177,644'Low-voltage fast-write PMOS NVSRAM cell'2015 9,177,658'1T1b and 2T2b flash-based, data-oriented EEPROM design'2015 9,171,627'Non-boosting program inhibit scheme in NAND design'2015 9,147,837'Resistive memory cell and method for forming a resistive memory cell'2015 9,142,284'Concurrent use of SRAM cells with both NMOS and PMOS pass gates in a memory system'2015 9,129,678'Method and apparatus for reforming a memory cell of a memory'2015 9,112,133'Resistive random access memory and method for controlling manufacturing of corresponding sub-resolution features of conductive and resistive elements'2015 9,087,595'Shielding 2-cycle half-page read and program schemes for advanced NAND flash design'2015 9,063,849'Different types of memory integrated in one chip by using a novel protocol'2015 9,047,945'Systems and methods for reading resistive random access memory (RRAM) cells'2015 9,042,162'SRAM cells suitable for Fin field-effect transistor (FinFET) process'2015 9,042,159'Configuring resistive random access memory (RRAM) array for write operations'2015 9,019,764'Low-voltage page buffer to be used in NVM design'2015 8,999,786'Reducing source contact to gate spacing to decrease transistor pitch'2015 9,001,583'On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation'2015 9,001,545'NOR-based BCAM/TCAM cell and array with NAND scalability'2015 8,996,785'NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface'2015 8,976,588'NVSRAM cells with voltage flash charger'2015 8,971,113'Pseudo-8T NVSRAM cell with a charge-follower'2015 8,964,470'Method and architecture for improving defect detectability, coupling area, and flexibility of NVSRAM cells and arrays'2015 8,947,909'System and method for creating a bipolar resistive RAM (RRAM)'2015 8,937,831'System and method for modifying activation of a sense amplifier'2015 8,934,285'Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell'2015 8,933,500'EEPROM-based, data-oriented combo NVM design'2015 8,933,749'Circuits and methods for calibrating offset in an amplifier'2015 8,929,136'8T NVSRAM cell and cell operations'2015 8,923,049'1T1b and 2T2b flash-based, data-oriented EEPROM design'2014 8,917,551'Flexible 2T-based fuzzy and certain matching arrays'2014 8,885,388'Apparatus and method for reforming resistive memory cells'2014 8,873,309'Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers'2014 8,837,221'Write bias condition for 2T-string NOR flash cell'2014 8,809,148'EEPROM-based, data-oriented combo NVM design'2014 8,773,903'High speed high density nand-based 2T-NOR flash memory design'2014 8,775,719'NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface'2014 8,634,241'Universal timing waveforms sets to improve random access read and write speed of memories'2014 8,634,254'Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction'2014 8,609,528'High-density patterning'2013 8,582,363'Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory'2013 8,559,232'DRAM-like NVM memory array and sense amplifier design for high temperature and high endurance operation'2013 8,531,885'NAND-based 2T2b NOR flash array with a diode connection to cell\'s source node for size reduction using the least number of metal layers'2013 8,472,251'Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device'2013 8,462,553'Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory'2013 8,455,923'Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device'2013 8,355,287'Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device'2013 8,345,481'NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array'2013 8,339,195'Circuits and methods for calibrating offset in an amplifier'2012 8,335,108'Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array'2012 8,331,150'Integrated SRAM and FLOTOX EEPROM memory device'2012 8,295,087'Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/âˆ’ 10v BVDS'2012 8,289,775'Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array'2012 8,274,829'Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/âˆ’ 10V BVDS'2012 8,237,212'Nonvolatile memory with a unified cell structure'2012 8,233,320'High speed high density NAND-based 2T-NOR flash memory design'2012 8,149,622'Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage'2012 8,120,966'Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory'2012 8,120,959'NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same'2012 8,072,811'NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array'2011 8,030,128'Method to form high density phase change memory (PCM) top contact every two bits'2011 7,994,052'High-density patterning'2011 7,985,616'Methods to form wide heater trenches and to form memory cells to engage heaters'2011 7,952,920'Phase change memory array circuits and methods of manufacture'2011 7,939,445'High density via and metal interconnect structures, and methods of forming the same'2011 7,939,414'Ion implantation and process sequence to form smaller base pick-up'2011 7,915,092'Nonvolatile memory with a unified cell structure'2011 7,888,166'Method to form high efficiency GST cell using a double heater cut'2011 7,863,709'Low base resistance bipolar junction transistor array'2011 7,855,912'Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell'2010 7,839,672'Phase change memory array circuits and methods of manufacture'2010 7,830,713'Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array'2010 7,807,539'Ion implantation and process sequence to form smaller base pick-up'2010 7,745,809'Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips'2010 7,709,835'Method to form high efficiency GST cell using a double heater cut'2010 7,688,612'Bit line structure for a multilevel, dual-sided nonvolatile memory cell array'2010 7,636,252'Nonvolatile memory with a unified cell structure'2009 7,609,538'Logic process DRAM'2009 7,596,011'Logic process DRAM'2009 7,372,736'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2008 7,369,438'Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications'2008 7,349,257'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'2008 7,339,824'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'2008 7,324,384'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2008 7,289,366'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2007 7,283,401'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2007 7,184,290'Logic process DRAM'2007 7,177,190'Combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications'2007 7,164,608'NVRAM memory cell architecture that integrates conventional SRAM and flash cells'2007 7,154,783'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'2006 7,149,120'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'2006 7,120,064'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2006 7,110,302'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2006 7,102,929'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2006 7,087,953'Unified non-volatile memory device and method for integrating NOR and NAND-type flash memory and EEPROM device on a single substrate'2006 7,075,826'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2006 7,064,978'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'2006 6,947,324'Logic process DRAM'2005 6,891,221'Array architecture and process flow of nonvolatile memory devices for mass storage applications'2005 6,862,223'MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT'2005 6,850,438'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'2005 6,839,278'Highly-integrated flash memory and mask ROM array architecture'2005 6,818,491'Set of three level concurrent word line bias conditions for a NOR type flash memory array'2004 6,788,611'Flash memory array structure suitable for multiple simultaneous operations'2004 6,788,612'Flash memory array structure suitable for multiple simultaneous operations'2004 6,777,292'Set of three level concurrent word line bias conditions for a NOR type flash memory array'2004 6,757,196'Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device'2004 6,717,846'Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration'2004 6,714,457'Parallel channel programming scheme for MLC flash memory'2004 6,687,154'Highly-integrated flash memory and mask ROM array architecture'2004 6,680,859'Logic process DRAM'2004 6,660,585'Stacked gate flash memory cell with reduced disturb conditions'2003 6,628,563'Flash memory array for multiple simultaneous operations'2003 6,620,682'Set of three level concurrent word line bias conditions for a nor type flash memory array'2003 6,584,034'Flash memory array structure suitable for multiple simultaneous operations'2003 6,574,152'Circuit design for accepting multiple input voltages for flash EEPROM memory operations'2003 6,570,781'Logic process DRAM'2003 6,563,742'Method to turn a flash memory into a versatile, low-cost multiple time programmable EPROM'2003 6,556,481'3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell'2003 6,515,910'Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM'2003 6,498,752'Three step write process used for a nonvolatile NOR type EEPROM memory'2002 6,381,670'Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation'2002 RE037419'Flash memory array and decoding architecture'2001 6,275,417'Multiple level flash memory'2001 6,262,622'Breakdown-free high voltage input circuitry'2001 6,258,668'Array architecture and process flow of nonvolatile memory devices for mass storage applications'2001 6,240,027'Approach to provide high external voltage for flash memory erase'2001 6,181,607'Reversed split-gate cell array'2001 6,166,961'Approach to provide high external voltage for flash memory erase'2000 6,160,737'Bias conditions for repair, program and erase operations of non-volatile memory'2000 6,134,150'Erase condition for flash memory'2000 6,031,765'Reversed split-gate cell array'2000 6,023,188'Positive/negative high voltage charge pump system'2000 6,009,022'Node-precise voltage regulation for a MOS memory system'1999 5,978,278'Flash memory having low threshold voltage distribution'1999 5,978,283'Charge pump circuits'1999 5,978,277'Bias condition and X-decoder circuit of flash memory array'1999 5,953,250'Flash memory array and decoding architecture'1999 5,953,255'Low voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced endurance'1999 5,930,826'Flash memory protection attribute status bits held in a flash memory array'1999 5,920,503'Flash memory with novel bitline decoder and sourceline latch'1999 5,917,757'Flash memory with high speed erasing structure using thin oxide semiconductor devices'1999 5,914,896'Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices'1999 5,882,123'Roll-formed bearing race and process for producing the same'1999 5,859,571'Frequency trimmable oscillator and frequency multiplier'1999 5,856,942'Flash memory array and decoding architecture'1999 5,856,945'Method for preventing sub-threshold leakage in flash memory cells to achieve accurate reading, verifying, and fast over-erased Vt correction'1999 5,848,000'Flash memory address decoder with novel latch structure'1998 5,835,420'Node-precise voltage regulation for a MOS memory system'1998 5,822,252'Flash memory wordline decoder with overerase repair'1998 5,796,657'Flash memory with flexible erasing size from multi-byte to multi-block'1998 5,777,924'Flash memory array and decoding architecture'1998 5,777,923'Flash memory read/write controller'1998 5,774,396'Flash memory with row redundancy'1998 5,768,193'Bit-refreshable method and circuit for refreshing a nonvolatile flash memory'1998 5,748,538'OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array'1998 5,748,545'Memory device with on-chip manufacturing and memory cell defect detection capability'1998 5,687,121'Flash EEPROM worldline decoder'1997 5,682,350'Flash memory with divided bitline'1997 5,646,890'Flexible byte-erase flash memory and decoder'1997 5,600,586'Flat-cell ROM and decoder'1997 5,572,462'Multistate prom and decompressor'1996 5,309,639'Method of making a machine component with lubricated wear surface'1994 4,817,030'CMOS full-adder stage'1989 4,731,570'Electrical drive circuit for a variable-speed switched reluctance motor'1988 4,721,598'Powder metal composite and method of its manufacture'1988 4,601,592'Tapered roller bearing capable of sustained operation without lubricant replenishment'1986 4,571,097'Tapered roller bearing with pressurized rib ring'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–1994Based in Canton, OH, US· patent location history

1996–2017Based in Saratoga, CA, US· patent location history

1998–2016Patents assigned to APLUS FLASH TECHNOLOGY INC (107)· patent assignee history

2003–2018Patents assigned to MARVELL INT LTD (26)· patent assignee history

2003–2015Based in Fremont, CA, US· patent location history

2009–2015Patents assigned to HSU FU-CHANG (28)· patent assignee history

2009Based in San Jose, CA, US· patent location history

2010–2020Patents assigned to MARVELL WORLD TRADE LTD (20)· patent assignee history

2011–2017Patents assigned to LEE PETER WUNG (37)· patent assignee history

2012–2020Based in Pleasanton, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
APLUS FLASH TECHNOLOGY INC	107	1998–2016
LEE PETER WUNGself	37	2011–2017
HSU FU-CHANG	28	2009–2015
MARVELL INT LTD	26	2003–2018
MARVELL WORLD TRADE LTD	20	2010–2020

Locations

Location	Patents	Span
Saratoga, California, US	136	1996–2017
Pleasanton, California, US	26	2012–2020
Fremont, California, US	20	2003–2015
Canton, OH, US	4	1986–1994
San Jose, California, US	1	2009