Inventor
CHUN-CHANG CHEN
Inventor
TW
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10BElectronic memory devices10%
H10DInorganic electric semiconductor devices10%
PatentTitleYear
12,165,867Method for reducing charging of semiconductor wafers202412,051,617Method of making a semiconductor device and semiconductor device202411,769,662Method for reducing charging of semiconductor wafers202311,665,897Improving surface topography by forming spacer-like components202311,450,557Poisoned metal layer with sloped sidewall for making dual damascene interconnect202211,276,699Surface topography by forming spacer-like components2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2024Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (6)· patent assignee history
2022–2024Patents assigned to TSMC NANJING COMPANY LTD (2)· patent assignee history
2022–2024Based in TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 6 | 2022–2024 |
| TSMC NANJING COMPANY LTD | 2 | 2022–2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 6 | 2022–2024 |