Inventor
George R. Canepa
Inventor
Folsom, CA, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores42%
G06FElectric digital data processing17%
G05FSystems for regulating electric or magnetic variables8%
G06NComputing arrangements based on specific computational models8%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems8%
H10BElectronic memory devices8%
H10DInorganic electric semiconductor devices8%
PatentTitleYear
5,532,915'Method and apparatus for providing an ultra low power regulated negative charge pump'19965,245,574'Apparatus for increasing the speed of operation of non-volatile memory arrays'19935,142,495'Variable load for margin mode'19925,055,897'Semiconductor cell for neural network and the like'19915,047,989'Chapter mode selection apparatus for MOS memory'19914,685,084'Apparatus for selecting alternate addressing mode and read-only memory'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1987–1996Patents assigned to INTEL CORP (6)· patent assignee history
1987Based in Orangevale, CA, US· patent location history
1991–1996Based in Folsom, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 6 | 1987–1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Folsom, California, US | 5 | 1991–1996 |
| Orangevale, California, US | 1 | 1987 |