Inventor
Joffre F. Bernard
Inventor
Santa Clara, CA, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1044%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H10NElectric solid-state devices not otherwise provided for6%
C25DProcesses for the electrolytic or electrophoretic production of coatings3%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
G01RMeasuring electric variables3%
H01GCapacitors3%
H10BElectronic memory devices3%
H10DInorganic electric semiconductor devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
8,373,148'Memory device with improved performance'20138,093,698'Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device'20127,790,497'Method to prevent alloy formation when forming layered metal oxides by metal oxidation'20106,811,671'Method of controlling zinc-doping in a copper-zinc alloy thin film electroplated on a copper surface and a semiconductor device thereby formed'20046,770,559'Method of forming wiring by implantation of seed layer material'20046,630,741'Method of reducing electromigration by ordering zinc-doping in an electroplated copper-zinc interconnect and a semiconductor device thereby formed'20036,624,074'Method of fabricating a semiconductor device by calcium doping a copper surface using a chemical solution'20036,621,165'Semiconductor device fabricated by reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface'20036,541,860'Barrier-to-seed layer alloying in integrated circuit interconnects'20036,541,286'Imaging of integrated circuit interconnects'20036,515,367'Sub-cap and method of manufacture therefor in integrated circuit capping layers'20036,479,898'Dielectric treatment in integrated circuit interconnects'20026,469,387'Semiconductor device formed by calcium doping a copper surface using a chemical solution'20026,465,867'Amorphous and gradated barrier layer for integrated circuit interconnects'20026,444,580'Method of reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface and semiconductor device thereby formed'20026,406,996'Sub-cap and method of manufacture therefor in integrated circuit capping layers'20026,309,959'Formation of self-aligned passivation for interconnect to minimize electromigration'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2004Patents assigned to ADVANCED MICRO DEVICES INC (13)· patent assignee history
2001–2013Based in Santa Clara, CA, US· patent location history
2002–2004Based in Redwood City, CA, US· patent location history
2010–2013Patents assigned to SPANSION LLC (3)· patent assignee history
2012–2013Patents assigned to BERNARD JOFFRE F (2)· patent assignee history
2012–2013Patents assigned to RATHOR MANUJ (2)· patent assignee history
2012Patents assigned to AVANZINO STEVEN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 13 | 2001–2004 |
| SPANSION LLC | 3 | 2010–2013 |
| BERNARD JOFFRE Fself | 2 | 2012–2013 |
| RATHOR MANUJ | 2 | 2012–2013 |
| AVANZINO STEVEN | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 10 | 2001–2013 |
| Redwood City, California, US | 7 | 2002–2004 |