Inventor
Xiao Hu Liu
Inventor
Briarcliff Manor, NY, US
Overview
Patents· 82 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H01LSemiconductor devices10%
Y10TTechnical subjects covered by former us classification10%
H10DInorganic electric semiconductor devices9%
H10NElectric solid-state devices not otherwise provided for5%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form3%
B81BMicrostructural devices or systems, e.g. micromechanical devices3%
B82YSpecific uses or applications of nanostructures3%
H01RElectrically-conductive connections3%
PatentTitleYear
10,997,764Method and apparatus for generating animation202110,847,475Advanced crack stop structure202010,840,194Advanced crack stop structure202010,840,195Advanced crack stop structure202010,622,220Nanofluidic channel fabrication by controlled spontaneous fracturing202010,546,809Wafer-scale power delivery202010,490,513Advanced crack stop structure201910,475,753Advanced crack stop structure201910,460,985Enhancement of iso-via reliability201910,388,567Thru-silicon-via structures201910,359,269Flexible electronics for wearable healthcare sensors201910,147,676Wafer-scale power delivery20189,941,472Piezoelectronic device with novel force amplification20189,812,359'Thru-silicon-via structures'20179,761,482'Enhancement of iso-via reliability'20179,738,560'Controlling fragmentation of chemically strengthened glass'20179,670,061'Flexible electronics for wearable healthcare sensors'20179,586,857'Controlling fragmentation of chemically strengthened glass'20179,565,759'Axiocentric scrubbing land grid array contacts and methods for fabrication'20179,536,842'Structure with air gap crack stop'20179,245,824'Through-vias for wiring layers of semiconductor devices'20169,236,325'Through-vias for wiring layers of semicondutor devices'20169,082,781'Semiconductor article having a zig-zag guard ring and method of forming the same'20159,040,841'Axiocentric scrubbing land grid array contacts and methods for fabrication'20158,969,174'Fixed curvature force loading of mechanically spalled films'20158,865,572'Dislocation engineering using a scanned laser'20148,865,571'Dislocation engineering using a scanned laser'20148,846,191'Thermal expansion control employing platelet fillers'20148,803,284'Thick on-chip high-performance wiring structures'20148,796,133'Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections'20148,765,595'Thick on-chip high-performance wiring structures'20148,679,943'Fixed curvature force loading of mechanically spalled films'20148,650,512'Elastic modulus mapping of an integrated circuit chip in a chip/device package'20148,624,152'Negative coefficient thermal expansion engineered particles for composite fabrication'20148,604,618'Structure and method for reducing vertical crack propagation'20138,492,802'Multiple orientation nanowires with gate stack sensors'20138,449,971'Thermal expansion control employing platelet fillers'20138,405,279'Coupling piezoelectric material generated stresses to devices formed in integrated circuits'20138,367,492'Multiple Orientation Nanowires with Gate Stack Sensors'20138,368,125'Multiple orientation nanowires with gate stack stressors'20138,362,596'Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same'20138,278,155'Reprogrammable fuse structure and method'20128,263,879'Axiocentric scrubbing land grid array contacts and methods for fabrication'20128,247,947'Coupling piezoelectric material generated stresses to devices formed in integrated circuits'20128,241,957'Negative thermal expansion system (NTES) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging'20128,237,150'Nanowire devices for enhancing mobility through stress engineering'20128,159,854'Piezo-effect transistor device and applications'20128,138,448'Negative coefficient thermal expansion engineered particles for composite fabrication'20128,138,066'Dislocation engineering using a scanned laser'20128,119,206'Negative coefficient of thermal expansion particles'20128,076,756'Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures'20117,989,233'Semiconductor nanowire with built-in stress'20117,960,808'Reprogrammable fuse structure and method'20117,955,955'Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures'20117,955,952'Crackstop structures and methods of making same'20117,947,907'Electronics structures using a sacrificial multi-layer hardmask scheme'20117,935,588'Enhanced transistor performance by non-conformal stressed layers'20117,902,541'Semiconductor nanowire with built-in stress'20117,883,919'Negative thermal expansion system (NTEs) device for TCE compensation in elastomer compsites and conductive elastomer interconnects in microelectronic packaging'20117,847,402'BEOL interconnect structures with improved resistance to stress'20107,848,135'Piezo-driven non-volatile memory cell with hysteretic resistance'20107,790,577'Crackstop structures and methods of making same'20107,678,673'Strengthening of a structure by infiltration'20107,622,737'Test structures for electrically detecting back end of the line failures and methods of making and using the same'20097,579,069'Negative coefficient of thermal expansion particles and method of forming the same'20097,556,979'Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging'20097,525,161'Strained MOS devices using source/drain epitaxy'20097,491,965'Heat-shielded low power PCM-based reprogrammable eFUSE device'20097,485,582'Hardmask for improved reliability of silicon based dielectrics'20097,456,098'Building metal pillars in a chip for structure support'20087,417,315'Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging'20087,394,089'Heat-shielded low power PCM-based reprogrammable EFUSE device'20087,388,273'Reprogrammable fuse structure and method'20087,371,684'Process for preparing electronics structures using a sacrificial multilayer hardmask scheme'20087,357,977'Ultralow dielectric constant layer with controlled biaxial stress'20087,335,980'Hardmask for reliability of silicon based dielectrics'20087,314,789'Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification'20087,276,787'Silicon chip carrier with conductive through-vias and method for fabricating same'20077,260,810'Method of extracting properties of back end of line (BEOL) chip architecture'20077,173,312'Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification'20077,067,902'Building metal pillars in a chip for structure support'20066,972,209'Stacked via-stud with improved reliability in copper metallurgy'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2020Patents assigned to IBM (76)· patent assignee history
2005–2012Based in Croton-on-Hudson, NY, US· patent location history
2008–2020Based in Briarcliff Manor, NY, US· patent location history
2011–2014Patents assigned to LIU XIAO HU (16)· patent assignee history
2012–2015Patents assigned to LIU XIAO H (6)· patent assignee history
2012–2013Patents assigned to CHIDAMBARRAO DURESETI (4)· patent assignee history
2012–2020Based in Yorktown Heights, NY, US· patent location history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history
2020Based in Pelham Manor, NY, US· patent location history
2021Based in Beijing, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 76 | 2005–2020 |
| LIU XIAO HUself | 16 | 2011–2014 |
| GLOBALFOUNDRIES INC | 6 | 2016–2019 |
| LIU XIAO Hself | 6 | 2012–2015 |
| CHIDAMBARRAO DURESETI | 4 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Briarcliff Manor, New York, US | 56 | 2008–2020 |
| Croton-on-Hudson, New York, US | 16 | 2005–2012 |
| Yorktown Heights, New York, US | 8 | 2012–2020 |
| Beijing, CN | 1 | 2021 |
| Pelham Manor, New York, US | 1 | 2020 |