Inventor
Alan H. Huggins
Inventor
Gilroy, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1045%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
H05KPrinted circuits10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
B65HHandling thin or filamentary material, e.g. sheets, webs, cables3%
G06FElectric digital data processing3%
G11CStatic stores3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
6,531,756'Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit'20036,486,527'Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter'20026,369,437'Vertical fuse structure for integrated circuits and a method of disconnecting the same'20026,346,748'Electronic circuit structure with photoresist layer that has non-precision openings formed by a laser'20026,311,316'Designing integrated circuit gate arrays using programmable logic device bitstreams'20016,228,564'Method of patterning photoresist using precision and non-precision techniques'20016,096,566'Inter-conductive layer fuse for integrated circuits'20006,080,533'Method of patterning photoresist using precision and non-precision techniques'20006,078,091'Inter-conductive layer fuse for integrated circuits'20006,060,330'Method of customizing integrated circuits by selective secondary deposition of interconnect material'20005,989,783'Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material'19995,986,319'Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit'19995,985,518'Method of customizing integrated circuits using standard masks and targeting energy beams'19995,953,577'Customization of integrated circuits'19995,949,323'Non-uniform width configurable fuse structure'19995,945,238'Method of making a reusable photolithography mask'19995,910,922'Method for testing data retention in a static random access memory using isolated V.sub.cc supply'19995,885,749'Method of customizing integrated circuits by selective secondary deposition of layer interconnect material'19995,840,627'Method of customizing integrated circuits using standard masks and targeting energy beams for single resist development'19985,514,613'Parallel manufacturing of semiconductor devices and the resulting structure'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996Patents assigned to INTEGRATED DEVICE TECHNOLOGY (1)· patent assignee history
1996–2002Based in Gilroy, CA, US· patent location history
1998–2003Patents assigned to CLEAR LOGIC INC (16)· patent assignee history
1999Patents assigned to INTEGRATED DEVICE TECH (1)· patent assignee history
2001Patents assigned to CLEAR LOGIC (1)· patent assignee history
2003Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CLEAR LOGIC INC | 16 | 1998–2003 |
| CLEAR LOGIC | 1 | 2001 |
| INTEGRATED DEVICE TECH | 1 | 1999 |
| INTEGRATED DEVICE TECHNOLOGY | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Gilroy, California, US | 19 | 1996–2002 |
| Santa Clara, California, US | 1 | 2003 |