Inventor
Shyam P. Murarka
Inventor
Clifton Park, NY, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
C25DProcesses for the electrolytic or electrophoretic production of coatings7%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations2%
B24BMachines, devices, or processes for grinding or polishing2%
B82YSpecific uses or applications of nanostructures2%
C07CAcyclic or carbocyclic compounds2%
C07DHeterocyclic compounds2%
PatentTitleYear
10,913,710Benzene disulfonamide for the treatment of cancer20217,285,842'Siloxane epoxy polymers as metal diffusion barriers to reduce electromigration'20077,202,159'Diffusion barriers comprising a self-assembled monolayer'20077,019,386'Siloxane epoxy polymers for low-k dielectric applications'20066,486,533'Metallization structures for microelectronic applications and process for forming the structures'20026,368,966'Metallization structures for microelectronic applications and process for forming the structures'20026,319,387'Copper alloy electroplating bath for microelectronic applications'20015,956,604'Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide'19995,637,185'Systems for performing chemical mechanical planarization and process for conducting same'1997RE032207'Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide'19864,522,842'Boron nitride X-ray masks with controlled stress'19854,502,209'Forming low-resistance contact to silicon'19854,378,628'Cobalt silicide metallization for semiconductor integrated circuits'19834,337,476'Silicon rich refractory silicides as gate metal'19824,332,839'Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide'19824,324,038'Method of fabricating MOS field effect transistors'19824,276,557'Integrated semiconductor circuit structure and method for making it'19814,149,905'Method of limiting stacking faults in oxidized silicon wafers'19794,134,125'Passivation of metallized semiconductor substrates'1979Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1979–1983Patents assigned to BELL TELEPHONE LABOR INC (7)· patent assignee history
1979Based in Murray Hill, NJ, US· patent location history
1981–1986Based in New Providence, NJ, US· patent location history
1982Based in New Brunswick, NJ, US· patent location history
1985Patents assigned to AT & T BELL LAB (2)· patent assignee history
1997–2007Patents assigned to RENSSELAER POLYTECH INST (4)· patent assignee history
1997–2007Based in Clifton Park, NY, US· patent location history
2001–2002Patents assigned to SEMITOOL INC (3)· patent assignee history
2021Patents assigned to MAX PLANCK GESELLSCHAFT (1)· patent assignee history
2021Based in West Bengal, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| BELL TELEPHONE LABOR INC | 7 | 1979–1983 |
| RENSSELAER POLYTECH INST | 4 | 1997–2007 |
| SEMITOOL INC | 3 | 2001–2002 |
| AT & T BELL LAB | 2 | 1985 |
| MAX PLANCK GESELLSCHAFT | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Clifton Park, New York, US | 8 | 1997–2007 |
| New Providence, New Jersey, US | 7 | 1981–1986 |
| Murray Hill, New Jersey, US | 2 | 1979 |
| West Bengal, IN | 1 | 2021 |
| New Brunswick, New Jersey, US | 1 | 1982 |