Inventor
Jan Hoentschel
Inventor
Dresden, DE
Overview
Patents· 174 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices42%
H01LSemiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10BElectronic memory devices1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
G06FElectric digital data processing1%
H10HInorganic light-emitting semiconductor devices having potential barriers1%
G02BOptical elements, systems or apparatus1%
G11CStatic stores1%
PatentTitleYear
10,644,152Buried-channel low noise transistors and methods of making such devices202010,580,863Transistor element with reduced lateral electrical field202010,340,380Three-dimensional transistor with improved channel mobility201910,283,490Communicating optical signals between stacked dies201910,157,996Methods for forming integrated circuits that include a dummy gate structure201810,056,376Ferroelectric FinFET20189,960,184FDSOI-capacitor20189,917,087'Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same'20189,881,841'Methods for fabricating integrated circuits with improved implantation processes'20189,806,067'Die-die stacking'20179,793,372'Integrated circuit including a dummy gate structure and method for the formation thereof'20179,735,174'FDSOI—capacitor'20179,698,179'Capacitor structure and method of forming a capacitor structure'20179,620,589'Integrated circuits and methods of fabrication thereof'20179,608,003'Integrated circuit product with bulk and SOI semiconductor devices'20179,608,112'BULEX contacts in advanced FDSOI techniques'20179,590,118'Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure'20179,583,240'Temperature independent resistor'20179,553,046'E-fuse in SOI configuration'20179,502,564'Fully depleted device with buried insulating layer in channel region'20169,490,344'Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process'20169,490,189'Semiconductor device comprising a stacked die configuration including an integrated peltier element'20169,472,642'Method of forming a semiconductor device structure and such a semiconductor device structure'20169,466,717'Complex semiconductor devices of the SOI type'20169,461,145'OPC enlarged dummy electrode to eliminate ski slope at eSiGe'20169,449,826'Graded well implantation for asymmetric transistors having reduced gate electrode pitches'20169,449,972'Ferroelectric FinFET'20169,443,945'Transistor including a gate electrode extending all around one or more channel regions'20169,443,871'Cointegration of bulk and SOI semiconductor devices'20169,431,508'Simplified gate-first HKMG manufacturing flow'20169,425,052'Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures'20169,425,318'Integrated circuits with fets having nanowires and methods of manufacturing the same'20169,412,859'Contact geometry having a gate silicon length decoupled from a transistor length'20169,412,848'Methods of forming a complex GAA FET device at advanced technology nodes'20169,406,565'Methods for fabricating integrated circuits with semiconductor substrate protection'20169,396,950'Low thermal budget schemes in semiconductor device fabrication'20169,391,176'Multi-gate FETs having corrugated semiconductor stacks and method of forming the same'20169,391,156'Embedded capacitor'20169,385,232'FD devices in advanced semiconductor techniques'20169,373,509'FINFET doping method with curvilnear trajectory implantation beam path'20169,373,720'Three-dimensional transistor with improved channel mobility'20169,343,374'Efficient main spacer pull back process for advanced VLSI CMOS technologies'20169,324,831'Forming transistors without spacers and resulting devices'20169,324,868'Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections'20169,324,869'Method of forming a semiconductor device and resulting semiconductor devices'20169,312,189'Methods for fabricating integrated circuits with improved implantation processes'20169,263,270'Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structure'20169,257,530'Methods of making integrated circuits and components thereof'20169,231,045'Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby'20169,224,655'Methods of removing gate cap layers in CMOS applications'20159,224,840'Replacement gate FinFET structures with high mobility channel'20159,218,976'Fully silicided gate formed according to the gate-first HKMG approach'20159,214,396'Transistor with embedded stress-inducing layers'20159,190,516'Method for a uniform compressive strain layer and device thereof'20159,184,095'Contact bars with reduced fringing capacitance in a semiconductor device'20159,177,803'HK/MG process flows for P-type semiconductor devices'20159,165,840'Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof'20159,136,266'Gate oxide quality for complex MOSFET devices'20159,129,843'Integrated inductor'20159,123,827'Methods for fabricating integrated circuits with fully silicided gate electrode structures'20159,123,825'Methods for fabricating FinFET integrated circuits using laser interference lithography techniques'20159,093,554'Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers'20159,087,716'Channel semiconductor alloy layer growth adjusted by impurity ion implantation'20159,076,815'Spacer stress relaxation'20159,054,207'Field effect transistors for a flash memory comprising a self-aligned charge storage region'20159,054,044'Method for forming a semiconductor device and semiconductor device structures'20159,048,336'Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures'20159,035,306'Adjusting configuration of a multiple gate transistor by controlling individual fins'20159,029,214'Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts'20159,012,956'Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe'20159,006,045'Transistor including a gate electrode extending all around one or more channel regions'20158,987,104'Method of forming spacers that provide enhanced protection for gate electrode structures'20158,975,704'Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations'20158,963,208'Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof'20158,962,429'Integrated circuits with improved spacers and methods for fabricating same'20158,951,873'Semiconductor devices having encapsulated stressor regions and related fabrication methods'20158,951,877'Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment'20158,936,977'Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations'20158,916,430'Methods for fabricating integrated circuits with the implantation of nitrogen'20148,872,272'Stress enhanced CMOS circuits and methods for their manufacture'20148,871,586'Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material'20148,835,936'Source and drain doping using doped raised source and drain regions'20148,828,834'Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process'20148,822,298'Performance enhancement in transistors by reducing the recessing of active regions and removing spacers'20148,815,741'Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material'20148,809,151'Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy'20148,791,509'Multiple gate transistor having homogenously silicided fin end portions'20148,790,973'Workfunction metal stacks for a final metal gate'20148,786,027'Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage'20148,772,878'Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material'20148,759,960'Semiconductor device comprising a stacked die configuration including an integrated Peltier element'20148,748,281'Enhanced confinement of sensitive materials of a high-K metal gate electrode structure'20148,703,578'Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations'20148,698,243'Semiconductor device with strain-inducing regions and method thereof'20148,673,728'Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors'20148,673,713'Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions'20148,669,151'High-K metal gate electrode structures formed at different process stages of a semiconductor device'20148,664,068'Low-diffusion drain and source regions in CMOS transistors for low power/high performance applications'20148,647,951'Implantation of hydrogen to improve gate insulation layer-substrate interface'20148,615,145'Semiconductor device comprising a buried waveguide for device internal optical communication'20138,609,533'Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts'20138,598,007'Methods of performing highly tilted halo implantation processes on semiconductor devices'20138,574,991'Asymmetric transistor devices formed by asymmetric spacers and tilted implantation'20138,574,981'Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same'20138,563,374'Strained semiconductor devices having asymmetrical heterojunction structures and methods for the fabrication thereof'20138,564,089'Electronic fuse structure formed using a metal gate electrode material stack configuration'20138,536,036'Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors'20138,536,034'Methods of forming stressed silicon-carbon areas in an NMOS transistor'20138,524,563'Semiconductor device with strain-inducing regions and method thereof'20138,524,566'Methods for the fabrication of integrated circuits including back-etching of raised conductive structures'20138,507,348'Field effect transistors for a flash memory comprising a self-aligned charge storage region'20138,508,008'Optical signal transfer in a semiconductor device by using monolithic opto-electronic components'20138,501,601'Drive current increase in field effect transistors by asymmetric concentration profile of alloy species of a channel semiconductor alloy'20138,471,342'Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof'20138,455,314'Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage'20138,450,124'Adjusting configuration of a multiple gate transistor by controlling individual fins'20138,450,163'Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach'20138,440,516'Method of forming a field effect transistor'20138,440,534'Threshold adjustment for MOS devices by adapting a spacer width prior to implantation'20138,440,530'Methods of forming highly scaled semiconductor devices using a disposable spacer technique'20138,426,262'Stress adjustment in stressed dielectric materials of semiconductor devices by stress relaxation based on radiation'20138,426,266'Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices'20138,415,221'Semiconductor devices having encapsulated stressor regions and related fabrication methods'20138,409,942'Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition'20138,404,550'Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement'20138,390,127'Contact trenches for enhancing stress transfer in closely spaced transistors'20138,377,761'SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device'20138,357,604'Work function adjustment in high-k gate stacks for devices of different threshold voltage'20138,338,894'Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch'20128,338,274'Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration'20128,338,885'Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes'20128,334,569'Transistor with embedded Si/Ge material having enhanced across-substrate uniformity'20128,329,551'Semiconductor device substrate with embedded stress region, and related fabrication methods'20128,329,531'Strain memorization in strained SOI substrates of semiconductor devices'20128,324,041'Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors'20128,318,564'Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation'20128,278,174'In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile'20128,274,120'Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions'20128,247,275'Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers'20128,198,152'Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials'20128,198,633'Stress transfer enhancement in transistors by a late gate re-crystallization'20128,183,100'Transistor with embedded SI/GE material having enhanced across-substrate uniformity'20128,183,101'Multiple gate transistor having fins with a length defined by the gate electrode'20128,158,482'Asymmetric transistor devices formed by asymmetric spacers and tilted implantation'20128,154,084'Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material'20128,143,133'Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes'20128,143,132'Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime'20128,138,050'Transistor device comprising an asymmetric embedded semiconductor alloy'20128,062,952'Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors'20118,039,342'Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal'20118,034,669'Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region'20118,030,148'Structured strained substrate for forming strained transistors with reduced thickness of active layer'20118,026,134'Recessed drain and source areas in combination with advanced silicide formation in transistors'20118,017,504'Transistor having a high-k metal gate stack and a compressively stressed channel'20118,018,260'Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation'20117,977,225'Reducing implant degradation in tilted implantations by shifting implantation masks'20117,943,462'Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer'20117,943,442'SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device'20117,863,171'SOI transistor having a reduced body potential and a method of forming the same'20117,855,118'Drive current increase in transistors by asymmetric amorphization implantation'20107,829,421'SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same'20107,763,505'Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations'20107,723,195'Method of forming a field effect transistor'20107,696,052'Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions'20107,659,213'Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same'20107,608,499'Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same'20097,586,153'Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors'20097,579,262'Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same'20097,510,926'Technique for providing stress sources in MOS transistors in close proximity to a channel region'20097,402,497'Transistor device having an increased threshold stability without drive current degradation'20087,399,663'Embedded strain layer in thin SOI transistors and a method of forming the same'20087,354,836'Technique for forming a strained transistor by a late amorphization and disposable spacers'20087,344,984'Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors'20087,329,571'Technique for providing multiple stress sources in NMOS and PMOS transistors'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2016Patents assigned to ADVANCED MICRO DEVICES INC (33)· patent assignee history
2008–2020Based in Dresden, DE· patent location history
2008–2009Based in Neustadt in Sachsen, DD· patent location history
2010–2020Patents assigned to GLOBALFOUNDRIES INC (136)· patent assignee history
2011–2016Patents assigned to HOENTSCHEL JAN (74)· patent assignee history
2011–2016Patents assigned to FLACHOWSKY STEFAN (26)· patent assignee history
2011Based in Sachsen, DE· patent location history
2012–2016Patents assigned to SCHEIPER THILO (33)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 136 | 2010–2020 |
| HOENTSCHEL JANself | 74 | 2011–2016 |
| ADVANCED MICRO DEVICES INC | 33 | 2008–2016 |
| SCHEIPER THILO | 33 | 2012–2016 |
| FLACHOWSKY STEFAN | 26 | 2011–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dresden, DE | 169 | 2008–2020 |
| Neustadt in Sachsen, DD | 4 | 2008–2009 |
| Sachsen, DE | 1 | 2011 |