Inventor

Michael J. Zierak

Inventor
Essex Junction, VT, US

Overview

40→
Patents
2005–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 40 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices43%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H01LSemiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
G06FElectric digital data processing2%
G01RMeasuring electric variables1%
PatentTitleYear
10,388,728Structures with an airgap and methods of forming such structures201910,062,711Wafers and device structures with body contacts201810,050,115Tapered gate oxide in LDMOS devices20189,893,157'Structures with contact trenches and isolation trenches'20189,799,652'Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure'20179,768,028'Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure'20179,721,948'Switch improvement using layout optimization'20179,595,579'Dual shallow trench isolation (STI) structure for field effect transistor (FET)'20179,383,404'High resistivity substrate final resistance test structure'20169,240,463'High voltage laterally diffused metal oxide semiconductor'20169,236,449'High voltage laterally diffused metal oxide semiconductor'20169,059,276'High voltage laterally diffused metal oxide semiconductor'20158,946,013'Lateral diffusion field effect transistor with drain region self-aligned to gate electrode'20158,796,108'Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode'20148,716,759'Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device'20148,492,866'Isolated Zener diode'20138,466,501'Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET'20138,278,197'Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device'20128,227,318'Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation'20128,193,563'High power device isolation and integration'20128,169,007'Asymmetric junction field effect transistor'20128,168,500'Double gate depletion mode MOSFET'20128,114,750'Lateral diffusion field effect transistor with drain region self-aligned to gate electrode'20128,017,995'Deep trench semiconductor structure and method'20117,977,714'Wrapped gate junction field effect transistor'20117,956,412'Lateral diffusion field effect transistor with a trench field plate'20117,943,445'Asymmetric junction field effect transistor'20117,902,606'Double gate depletion mode MOSFET'20117,886,240'Modifying layout of IC based on function of interconnect and related circuit and design structure'20117,829,945'Lateral diffusion field effect transistor with asymmetric gate dielectric profile'20107,825,441'Junction field effect transistor with a hyperabrupt junction'20107,807,562'Dendrite growth control circuit'20107,781,292'High power device isolation and integration'20107,473,643'Dendrite growth control circuit'20097,348,251'Modulated trigger device'20087,326,987'Non-continuous encapsulation layer for MIM capacitor'20087,214,593'Passivation for improved bipolar yield'20077,109,584'Dendrite growth control circuit'20066,975,015'Modulated trigger device'20056,913,965'Non-Continuous encapsulation layer for MIM capacitor'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2018Patents assigned to IBM (33)· patent assignee history
2005–2018Based in Essex Junction, VT, US· patent location history
2011–2019Based in Colchester, VT, US· patent location history
2012–2015Patents assigned to ZIERAK MICHAEL J (8)· patent assignee history
2012–2013Patents assigned to PHELPS RICHARD A (4)· patent assignee history
2012–2015Patents assigned to FEILCHENFELD NATALIE B (3)· patent assignee history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (11)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM332005–2018
GLOBALFOUNDRIES INC112016–2019
ZIERAK MICHAEL Jself82012–2015
PHELPS RICHARD A42012–2013
FEILCHENFELD NATALIE B32012–2015
Locations
LocationPatentsSpan
Essex Junction, VT, US232005–2018
Colchester, VT, US172011–2019