Inventor
Mark B. Fuselier
Inventor
Austin, TX, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices44%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1041%
G01RMeasuring electric variables6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G11CStatic stores3%
PatentTitleYear
7,544,999'SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate'20097,432,136'Transistors with controllable threshold voltages, and various methods of making and operating same'20087,335,568'Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same'20087,180,136'Biased, triple-well fully depleted SOI structure'20077,176,095'Bi-modal halo implantation'20077,129,142'Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same'20066,919,236'Biased, triple-well fully depleted SOI structure, and various methods of making and operating same'20056,884,702'Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate'20056,876,037'Fully-depleted SOI device'20056,806,111'Semiconductor component and method of manufacture'20046,794,256'Method for asymmetric spacer formation'20046,780,686'Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions'20046,737,332'Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same'20046,583,016'Doped spacer liner for improved transistor performance'20036,570,228'Method and apparatus for electrically measuring insulating film thickness'20036,463,570'Apparatus and method for verifying process integrity'20026,426,262'Method of analyzing the effects of shadowing of angled halo implants'20026,410,350'Detecting die speed variations'20026,287,877'Electrically quantifying transistor spacer width'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2009Patents assigned to ADVANCED MICRO DEVICES INC (19)· patent assignee history
2001–2009Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 19 | 2001–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 19 | 2001–2009 |