Inventor

Arup Bhattacharyya

Inventor
Essex Junction, VT, US

Overview

209→
Patents
1976–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 209 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices32%
H10BElectronic memory devices16%
G11CStatic stores16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
B82YSpecific uses or applications of nanostructures6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H01LSemiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
C23CCoating metallic material3%
H01GCapacitors2%
PatentTitleYear
11,087,842Multifunctional memory cells202110,998,042Memory cells with tunneling materials including lanthanum oxide202110,957,389Multifunctional memory cells202110,892,340Memory cell structures202110,811,424Integrated computing structures formed on silicon202010,797,053Gated diode memory cells202010,741,658Memory configurations202010,566,053Memory cells programmed via multi-mechanism charge transports202010,546,639Multifunctional memory cells202010,541,027Multifunctional memory cells202010,483,155Trench isolation interfaces201910,411,026Integrated computing structures formed on silicon201910,374,101Memory arrays201910,297,493Trench isolation interfaces201910,276,576Gated diode memory cells201910,262,736Multifunctional memory cells201910,176,870Multifunctional memory cells201910,153,348Memory configurations201810,153,039Memory cells programmed via multi-mechanism charge transports201810,153,381Memory cells having an access gate and a control gate and dielectric stacks above and below the access gate20189,379,241'Semiconductor device with strained channels'20169,231,047'Capacitors and methods with praseodymium oxide insulators'20169,076,867'Semiconductor device structures including strained transistor channels'20158,951,880'Dielectrics containing at least one of a refractory metal or a non-refractory metal'20158,912,587'Scalable multi-functional and multi-level nano-crystal non-volatile memory device'20148,865,559'Capacitors and methods with praseodymium oxide insulators'20148,802,526'Methods of forming reverse mode non-volatile memory cell structures'20148,772,851'Dielectrics containing at least one of a refractory metal or a non-refractory metal'20148,759,170'Hafnium tantalum oxynitride dielectric'20148,679,928'Methods for stressing transistor channels of a semiconductor device structure'20148,637,377'Capacitors and methods with praseodymium oxide insulators'20148,557,672'Dielectrics containing at least one of a refractory metal or a non-refractory metal'20138,530,951'Scalable multi-functional and multi-level nano-crystal non-volatile memory device'20138,519,466'Tantalum silicon oxynitride high-K dielectrics and metal gates'20138,466,016'Hafnium tantalum oxynitride dielectric'20138,462,557'Methods of operating memory cell having asymmetric band-gap tunnel insulator using direct tunneling'20138,415,715'Discrete trap non-volatile multi-functional memory device'20138,399,332'Lanthanide dielectric with controlled interfaces'20138,319,272'Solar cell systems'20128,294,224'Devices and methods to improve carrier mobility'20128,293,611'Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels'20128,288,264'Scalable multi-function and multi-level nano-crystal non-volatile memory device'20128,242,554'Integrated two device non-volatile memory'20128,228,743'Memory cells containing charge-trapping zones'20128,193,568'Nanocrystal based universal memory cells, and memory cells'20128,168,502'Tantalum silicon oxynitride high-K dielectrics and metal gates'20128,159,875'Methods of storing multiple data-bits in a non-volatile memory cell'20128,153,497'Lanthanide dielectric with controlled interfaces'20128,143,657'Discrete trap non-volatile multi-functional memory device'20128,129,243'Methods of forming non-volatile memory having tunnel insulator of increasing conduction band offset'20128,125,003'High-performance one-transistor memory cell'20128,114,763'Tantalum aluminum oxynitride high-K dielectric'20128,084,370'Hafnium tantalum oxynitride dielectric'20118,063,436'Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material'20118,062,945'Methods of forming non-volatile memory structure with crested barrier tunnel layer'20118,058,118'Methods of forming and operating back-side trap non-volatile memory cells'20117,989,362'Hafnium lanthanide oxynitride films'20117,968,402'Method for forming a high-performance one-transistor memory cell'20117,968,960'Methods of forming strained semiconductor channels'20117,964,909'Scalable high density non-volatile memory cells in a contactless memory array'20117,956,426'Lanthanide dielectric with controlled interfaces'20117,902,582'Tantalum lanthanide oxynitride films'20117,898,850'Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells'20117,898,022'Scalable multi-functional and multi-level nano-crystal non-volatile memory device'20117,875,529'Semiconductor devices'20117,867,850'Enhanced multi-bit non-volatile memory device with resonant tunnel barrier'20117,851,827'Back-side trapped non-volatile memory device'20107,851,850'Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection'20107,838,362'Method of making an embedded trap direct tunnel non-volatile memory'20107,833,914'Capacitors and methods with praseodymium oxide insulators'20107,829,938'High density NAND non-volatile memory device'20107,786,516'Discrete trap non-volatile multi-functional memory device'20107,776,765'Tantalum silicon oxynitride high-k dielectrics and metal gates'20107,768,062'Combined volatile and non-volatile memory device with graded composition insulator stack'20107,759,747'Tantalum aluminum oxynitride high-κ dielectric'20107,759,715'Memory cell comprising dynamic random access memory (DRAM) nanoparticles and nonvolatile memory (NVM) nanoparticle'20107,749,848'Band-engineered multi-gated non-volatile memory device with enhanced attributes'20107,750,395'Scalable Flash/NV structures and devices with extended endurance'20107,728,350'Memory cell with negative differential resistance'20107,723,166'Optoelectronic devices and solar cells'20107,687,402'Methods of making optoelectronic devices, and methods of making solar cells'20107,671,407'Embedded trap direct tunnel non-volatile memory'20107,662,693'Lanthanide dielectric with controlled interfaces'20107,660,144'High-performance one-transistor memory cell'20107,635,630'Scalable high density non-volatile memory cells in a contactless memory array'20097,629,641'Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection'20097,625,803'Memory devices, electronic systems, and methods of forming memory devices'20097,612,403'Low power non-volatile memory and gate stack'20097,605,030'Hafnium tantalum oxynitride high-k dielectric and metal gates'20097,579,242'High performance multi-level non-volatile memory device'20097,566,601'Method of making a one transistor SOI non-volatile random access memory cell'20097,563,730'Hafnium lanthanide oxynitride films'20097,553,735'Scalable high performance non-volatile memory cells using multi-mechanism carrier transport'20097,550,824'Low k interconnect dielectric using surface transformation'20097,544,990'Scalable integrated logic and non-volatile memory'20097,544,604'Tantalum lanthanide oxynitride films'20097,528,043'Scalable gate and storage dielectric'20097,525,149'Combined volatile and non-volatile memory device with graded composition insulator stack'20097,492,030'Techniques to create low K ILD forming voids between metal lines'20097,492,042'Integrated circuit cooling and insulating device and method'20097,485,504'Stable PD-SOI devices and methods'20097,485,513'One-device non-volatile random access memory cell'20097,485,497'Integrated circuit cooling and insulating device and method'20097,482,651'Enhanced multi-bit non-volatile memory device with resonant tunnel barrier'20097,476,927'Scalable multi-functional and multi-level nano-crystal non-volatile memory device'20097,459,740'Integrated DRAM-NVRAM multi-level memory'20087,457,159'Integrated DRAM-NVRAM multi-level memory'20087,456,054'Gated lateral thyristor-based random access memory cell (GLTRAM)'20087,442,633'Decoupling capacitor for high frequency noise immunity'20087,440,317'One transistor SOI non-volatile random access memory cell'20087,440,310'Memory cell with trenched gated thyristor'20087,436,018'Discrete trap non-volatile multi-functional memory device'20087,432,562'SRAM devices, and electronic systems comprising SRAM devices'20087,432,548'Silicon lanthanide oxynitride films'20087,429,767'High performance multi-level non-volatile memory device'20087,417,893'Integrated DRAM-NVRAM multi-level memory'20087,402,850'Back-side trapped non-volatile memory device'20087,403,419'Integrated DRAM-NVRAM multi-level memory'20087,403,416'Integrated DRAM-NVRAM multi-level memory'20087,400,012'Scalable Flash/NV structures and devices with extended endurance'20087,385,245'Low power memory subsystem with progressive non-volatility'20087,379,336'Integrated DRAM-NVRAM multi-level memory'20087,378,707'Scalable high density non-volatile memory cells in a contactless memory array'20087,365,388'Embedded trap direct tunnel non-volatile memory'20087,361,559'Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region'20087,358,131'Methods of forming SRAM constructions'20087,351,620'Methods of forming semiconductor constructions'20087,349,252'Integrated DRAM-NVRAM multi-level memory'20087,345,299'Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon Enriched floating charge trapping media over the crystalline layer'20087,339,830'One transistor SOI non-volatile random access memory cell'20087,304,380'Integrated circuit cooling and insulating device and method'20077,300,821'Integrated circuit cooling and insulating device and method'20077,291,519'Methods of forming transistor constructions'20077,288,819'Stable PD-SOI devices and methods'20077,285,798'CMOS inverter constructions'20077,279,740'Band-engineered multi-gated non-volatile memory device with enhanced attributes'20077,276,760'Low power memory subsystem with progressive non-volatility'20077,273,784'Scalable high density non-volatile memory cells in a contactless memory array'20077,268,022'Stable PD-SOI devices and methods'20077,268,030'Methods of forming semiconductor constructions'20077,250,338'Scalable Flash/NV structures and devices with extended endurance'20077,250,628'Memory devices and electronic systems comprising thyristors'20077,244,981'Scalable high performance non-volatile memory cells using multi-mechanism carrier transport'20077,229,865'Methods of making semiconductor-on-insulator thin film transistor constructions'20077,224,002'Silicon on insulator read-write non-volatile memory comprising lateral thyristor and trapping layer'20077,221,026'Computer systems containing resistors which include doped silicon/germanium'20077,208,793'Scalable integrated logic and non-volatile memory'20077,190,028'Semiconductor-on-insulator constructions'20077,190,043'Techniques to create low K ILD for beol'20077,183,611'SRAM constructions, and electronic systems comprising SRAM constructions'20077,184,312'One transistor SOI non-volatile random access memory cell'20077,176,073'Methods of forming memory cells having diodes and electrode plates connected to source/drain regions'20077,166,888'Scalable high density non-volatile memory cells in a contactless memory array'20077,158,401'Methods for machine detection of at least one aspect of an object, methods for machine identification of a person, and methods of forming electronic systems'20077,158,410'Integrated DRAM-NVRAM multi-level memory'20077,157,387'Techniques to create low K ILD for BEOL'20077,151,037'Processes of forming stacked resistor constructions'20067,148,544'Semiconductor-on-insulator constructions'20067,145,186'Memory cell with trenched gated thyristor'20067,132,348'Low k interconnect dielectric using surface transformation'20067,130,216'One-device non-volatile random access memory cell'20067,115,948'Transistor constructions and electronic devices'20067,072,223'Asymmetric band-gap engineered nonvolatile memory device'20067,042,052'Transistor constructions and electronic devices'20067,042,027'Gated lateral thyristor-based random access memory cell (GLTRAM)'20067,026,690'Memory devices and electronic systems comprising integrated bipolar and FET devices'20067,019,378'Field-shielded SOI-MOS structure free from floating body effects, and method of fabrication therefor'20067,015,530'Electronic systems comprising memory devices'20067,012,297'Scalable flash/NV structures and devices with extended endurance'20066,998,667'Scalable gate and storage dielectric'20066,998,683'TFT-based common gate CMOS inverters, and computer systems utilizing novel CMOS inverters'20066,982,457'Semiconductor devices, and electronic systems comprising semiconductor devices'20066,979,880'Scalable high performance antifuse structure and process'20056,958,263'Methods of forming devices, constructions and systems comprising thyristors'20056,955,960'Decoupling capacitor for high frequency noise immunity'20056,950,340'Asymmetric band-gap engineered nonvolatile memory device'20056,943,065'Scalable high performance antifuse structure and process'20056,933,572'Field-shielded SOI-MOS structure free from floating body effect, and method of fabrication therefor'20056,917,078'One transistor SOI non-volatile random access memory cell'20056,908,798'Methods of making semiconductor-on-insulator thin film transistor constructions'20056,903,969'One-device non-volatile random access memory cell'20056,903,001'Techniques to create low K ILD for BEOL'20056,900,667'Logic constructions and electronic devices'20056,888,200'One transistor SOI non-volatile random access memory cell'20056,882,010'High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters'20056,873,015'Semiconductor constructions comprising three-dimensional thin film transistor devices and resistors'20056,873,018'Memory cell constructions comprising integrated bipolar and FET devices'20056,845,034'Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons'20056,828,632'Stable PD-SOI devices and methods'20046,812,504'TFT-based random access memory cells comprising thyristors'20046,808,971'High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters'20046,800,892'Memory devices, and electronic systems comprising memory devices'20046,784,480'Asymmetric band-gap engineered nonvolatile memory device'20046,768,156'Non-volatile random access memory cells associated with thin film constructions'20046,759,712'Semiconductor-on-insulator thin film transistor constructions'20046,743,681'Methods of Fabricating Gate and Storage Dielectric Stacks having Silicon-Rich-Nitride'20046,713,810'Non-volatile devices, and electronic systems comprising non-volatile devices'20046,700,771'Decoupling capacitor for high frequency noise immunity'20046,344,373'Antifuse structure and process'20025,874,778'Embedded power and ground plane structure'19995,811,870'Antifuse structure'19984,870,470'Non-volatile memory cell having Si rich silicon nitride charge trapping layer'19894,776,922'Formation of variable-width sidewall structures'19884,648,179'Process of making interconnection structure for semiconductor device'19874,488,262'Electronically programmable read only memory'19844,333,808'Method for manufacture of ultra-thin film capacitor'19824,190,466'Method for making a bipolar transistor structure utilizing self-passivating diffusion sources'19804,094,057'Field effect transistor lost film fabrication process'19783,978,577'Fixed and variable threshold N-channel MNOSFET integration technique'1976

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1976–2002Patents assigned to IBM (11)· patent assignee history
1976–2021Based in Essex Junction, VT, US· patent location history
1980Based in Essex Center, VT, US· patent location history
2004–2021Patents assigned to MICRON TECHNOLOGY INC (196)· patent assignee history
2005Based in Chittenden County, VT, US· patent location history
2009–2015Based in Essex, VT, US· patent location history
2011–2014Patents assigned to BHATTACHARYYA ARUP (28)· patent assignee history
2011–2014Patents assigned to FORBES LEONARD (10)· patent assignee history
2011–2014Patents assigned to AHN KIE Y (7)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC1962004–2021
BHATTACHARYYA ARUPself282011–2014
IBM111976–2002
FORBES LEONARD102011–2014
AHN KIE Y72011–2014
Locations
LocationPatentsSpan
Essex Junction, VT, US2031976–2021
Essex, VT, US42009–2015
Chittenden County, VT, US12005
Essex Center, VT, US11980