Inventor

Hsien-Ming Tu

Inventor

Zhubei City, TW

Overview

28→

Patents

2015–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 28 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1042%

H01LSemiconductor devices40%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

H10DInorganic electric semiconductor devices3%

A61BDiagnosis1%

B23KSoldering or unsoldering1%

F16JPistons1%

H01FMagnets1%

H02JElectric power networks1%

H04BTransmission1%

PatentTitleYear

11,107,772Semiconductor package and method of manufacturing semiconductor package2021 10,985,121Bump structure and fabricating method thereof2021 10,879,198Package with solder regions aligned to recesses2020 10,854,564Semiconductor device and manufacturing method thereof2020 10,825,804Hollow metal pillar packaging scheme2020 10,497,646Dual-mode wireless charging device2019 10,354,986Hollow metal pillar packaging scheme2019 10,269,737Method for manufacturing semiconductor structure2019 10,262,958Package with solder regions aligned to recesses2019 10,163,828Semiconductor device and fabricating method thereof2018 10,062,654Semicondcutor structure and semiconductor manufacturing process thereof2018 10,032,737Semiconductor device and manufacturing method thereof2018 9,943,239Optical sensing system and associated electronic device2018 9,947,630Package with solder regions aligned to recesses2018 9,852,985Conductive terminal on integrated circuit2017 9,812,434'Hollow metal pillar packaging scheme'2017 9,799,615'Package structures having height-adjusted molding members and methods of forming the same'2017 9,786,618'Semiconductor structure and manufacturing method thereof'2017 9,748,212'Shadow pad for post-passivation interconnect structures'2017 9,679,883'Hollow metal pillar packaging scheme'2017 9,640,498'Integrated fan-out (InFO) package structures and methods of forming same'2017 9,627,332'Integrated circuit structure and seal ring structure'2017 9,559,044'Package with solder regions aligned to recesses'2017 9,484,318'Semiconductor device and manufacturing method thereof'2016 9,461,106'MIM capacitor and method forming the same'2016 9,343,417'Hollow metal pillar packaging scheme'2016 9,318,456'Self-alignment structure for wafer level chip scale package'2016 9,048,149'Self-alignment structure for wafer level chip scale package'2015

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (27)· patent assignee history

2015–2020Based in Zhubei City, TW· patent location history

2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history

2016–2021Based in Hsinchu County, TW· patent location history

2019Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	27	2015–2021
TAIWAN SEMICONDUCTOR MFG	1	2016

Locations

Location	Patents	Span
Zhubei City, TW	15	2015–2020
Hsinchu County, TW	12	2016–2021
Hsinchu, TW	1	2019