Inventor
ANTON J. DEVILLIERS
Inventor
US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices10%
H10DInorganic electric semiconductor devices8%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
H10BElectronic memory devices4%
G06TImage data processing or generation, in general3%
G06VImage or video recognition or understanding3%
H04NPictorial communication, e.g. television3%
PatentTitleYear
12,564,027Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals202612,541,155Coaxial see-through inspection system202612,529,965Method for selective exposure of wafer to corrective irradiation at a per-die level202612,505,998—202512,500,085Wet-dry bilayer resist202512,488,989Method to form narrow slot contacts202512,455,511In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones202512,381,093Hybrid patterning-bonding semiconductor tool202512,374,562Wafer shape control for W2W bonding202512,327,726Wet-dry bilayer resist dual tone exposure202512,276,922Backside deposition tuning of stress to control wafer bow in semiconductor processing202512,249,508Selective patterning with wet-dry bilayer resist202512,040,271Power delivery network for CFET with buried power rails202412,020,990Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks202412,001,147Precision multi-axis photolithography alignment correction using stressor film202411,990,334Method for tuning stress transitions of films on a substrate202411,966,171Method for producing overlay results with absolute reference for semiconductor manufacturing202411,901,360Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory202411,883,837System and method for liquid dispense and coverage control202411,862,497Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking202411,854,806Method for pattern reduction using a staircase spacer202311,841,617Method of forming a narrow trench202311,810,854Multi-dimensional vertical switching connections for connecting circuit elements202311,776,812Method for pattern reduction using a staircase spacer202311,721,551Localized stress regions for three-dimension chiplet formation202311,694,957Programmable connection segment and method of forming the same202311,688,642Localized stress regions for three-dimension chiplet formation202311,682,559Method to form narrow slot contacts202311,676,968Coaxial contacts for 3D logic and memory202311,640,118Method of pattern alignment for field stitching202311,640,937Horizontal programmable conducting bridges between conductive lines202311,630,397Method for producing overlay results with absolute reference for semiconductor manufacturing202311,631,6713D complementary metal oxide semiconductor (CMOS) device and method of forming the same202311,616,020Power distribution network for 3D logic and memory202311,616,053Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device202311,526,088Coaxial see-through alignment imaging system202211,513,445Tunable wavelength see-through layer stack202211,484,993Substrate holding apparatus and method for shape metrology202211,460,775Method and system for prevention of metal contamination by using a self-assembled monolayer coating202211,444,082Semiconductor apparatus having stacked gates and method of manufacture thereof202211,335,599Self-aligned contacts for 3D logic and memory202211,335,566Method for planarization of spin-on and CVD-deposited organic films202211,264,274Reverse contact and silicide process for three-dimensional logic devices202211,264,289Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks202211,247,309Substrate holding apparatus and method for shape metrology202211,251,200Coaxial contacts for 3D logic and memory202211,217,583Architecture design of monolithically integrated 3D CMOS logic and memory202211,201,148Architecture for monolithic 3D integration of semiconductor devices202111,201,051Method for layer by layer growth of conformal films2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TOKYO ELECTRON LTD (49)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOKYO ELECTRON LTD | 49 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 49 | 2021–2026 |