Inventor
Min-Chie Jeng
Inventor
Taipei, TW
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H01LSemiconductor devices21%
H10DInorganic electric semiconductor devices17%
H01FMagnets9%
G06FElectric digital data processing8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
Y10TTechnical subjects covered by former us classification5%
G01RMeasuring electric variables3%
H05KPrinted circuits3%
H01PWaveguides2%
PatentTitleYear
10,971,296Compact vertical inductors extending in vertical planes202110,860,769Method and system for integrated circuit design with on-chip variation and spatial correlation202010,840,201Methods and apparatus for transmission lines in packages202010,714,441Filter and capacitor using redistribution layer and micro bump layer202010,665,380Compact vertical inductors extending in vertical planes202010,629,756Semiconductor structure202010,521,538Method and system for integrated circuit design with on-chip variation and spatial correlation201910,276,295Compact vertical inductors extending in vertical planes201910,269,746Methods and apparatus for transmission lines in packages201910,216,879Method for establishing aging model of device and analyzing aging state of device with aging model201910,019,545Simulation scheme including self heating effect20189,960,133Filter and capacitor using redistribution layer and micro bump layer20189,923,101'Semiconductor structure'20189,653,531'Methods of manufacturing a package'20179,633,940'Structure and method for a high-K transformer with capacitive coupling'20179,559,053'Compact vertical inductors extending in vertical planes'20179,530,705'4 port L-2L de-embedding method'20169,472,612'Integrated capacitor'20169,449,917'Method of forming an inductor with magnetic material'20169,449,945'Filter and capacitor using redistribution layer and micro bump layer'20169,385,246'Differential MOSCAP device'20169,331,013'Integrated capacitor'20169,203,146'Antenna using through-silicon via'20159,171,798'Methods and apparatus for transmission lines in packages'20159,147,020'Transmission line characterization using EM calibration'20159,141,735'Circuit device reliability simulation system'20159,121,891'Apparatus and methods for de-embedding through substrate vias'20159,087,838'Structure and method for a high-K transformer with capacitive coupling'20159,041,152'Inductor with magnetic material'20158,941,212'Helical spiral inductor between stacking die'20158,901,714'Transmission line formed adjacent seal ring'20148,901,752'Tuning the efficiency in the transmission of radio-frequency signals using micro-bumps'20148,896,094'Methods and apparatus for inductors and transformers in packages'20148,860,114'Structure and method for a fishbone differential capacitor'20148,809,073'Apparatus and methods for de-embedding through substrate vias'20148,754,818'Integrated antenna structure on separate semiconductor die'20148,686,507'System and method for I/O ESD protection with floating and/or biased polysilicon regions'20148,674,883'Antenna using through-silicon via'20148,502,620'Balun system and method'20138,399,961'Tuning the efficiency in the transmission of radio-frequency signals using micro-bumps'20138,370,774'Constructing mapping between model parameters and electrical parameters'20138,319,286'System and method for input pin ESD protection with floating and/or biased polysilicon regions'20128,283,726'System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors'20127,933,747'Method and system for simulating dynamic behavior of a transistor'20117,642,602'System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2015Based in Keelung, TW· patent location history
2011–2014Based in Cupertino, CA, US· patent location history
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (18)· patent assignee history
2013–2017Patents assigned to JENG MIN-CHIE (11)· patent assignee history
2013–2017Patents assigned to KUO CHIN-WEI (8)· patent assignee history
2013–2017Patents assigned to YEN HSIAO-TSUNG (8)· patent assignee history
2013–2021Based in Taipei, TW· patent location history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (21)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 21 | 2016–2021 |
| TAIWAN SEMICONDUCTOR MFG | 18 | 2013–2016 |
| JENG MIN-CHIEself | 11 | 2013–2017 |
| KUO CHIN-WEI | 8 | 2013–2017 |
| YEN HSIAO-TSUNG | 8 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 38 | 2013–2021 |
| Keelung, TW | 4 | 2010–2015 |
| Cupertino, California, US | 3 | 2011–2014 |