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Inventor

Hiroshige Hirano

Inventor
Nara, JP

Overview

80→
Patents
1992–2017
Patent span
Physics
Primary field (CPC G)

Patents· 80 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores43%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H03KPulse technique9%
H10BElectronic memory devices7%
H10DInorganic electric semiconductor devices6%
G01RMeasuring electric variables4%
G06FElectric digital data processing4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H01LSemiconductor devices3%
G05FSystems for regulating electric or magnetic variables3%
PatentTitleYear
9,698,096'Semiconductor device'20179,673,139'Semiconductor device'20179,245,845'Semiconductor device'20168,841,753'Semiconductor device having seal wiring'20148,810,039'Semiconductor device having a pad and plurality of interconnects'20148,736,067'Semiconductor device having a pad'20148,710,667'Semiconductor device'20148,421,236'Semiconductor device'20138,421,233'Semiconductor device'20138,344,515'Semiconductor device'20138,338,958'Semiconductor device and manufacturing method thereof'20128,237,281'Semiconductor device'20128,164,163'Semiconductor device having sealing ring'20128,102,056'Semiconductor device having pads and which minimizes defects due to bonding and probing processes'20128,044,482'Semiconductor device'20117,888,801'Semiconductor device'2011RE041879'Semiconductor memory device'20107,696,607'Semiconductor device'20107,642,583'Ferroelectric memory device'20107,538,433'Semiconductor device'20097,521,801'Semiconductor device'20097,468,900'Semiconductor memory device having a bitline amplified to a positive voltage and a negative voltage'20087,372,314'Voltage level conversion circuit'20087,307,866'Ferroelectric memory and method for reading data from the ferroelectric memory'20077,280,406'Semiconductor memory device'20077,265,583'Voltage level conversion circuit'20077,184,344'Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch'20077,136,313'Semiconductor storage device'20067,110,314'Semiconductor memory device and method for initializing the same'20067,106,631'Semiconductor device'20067,092,275'Memory device of ferro-electric'20067,006,399'Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch'20066,912,149'Ferroelectric memory device and method for reading data from the same'20056,888,759'Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch'20056,882,193'Voltage detection circuit, power-on/off reset circuit, and semiconductor device'20056,872,998'Ferroelectric memory device'20056,822,493'Voltage detection circuit, power-on/off reset circuit, and semiconductor device'20046,538,482'Voltage detection circuit, power-on/off reset circuit, and semiconductor device'20036,449,183'Ferroelectric memory system and method of driving the same'20026,420,743'Semiconductor device'20026,353,550'Ferroelectric memory device'20026,246,624'Voltage detection circuit power-on/off reset circuit and semiconductor device'20016,163,043'Semiconductor device'20006,157,563'Ferroelectric memory system and method of driving the same'20006,118,688'Ferroelectric memory device and method for driving it'20006,081,036'Semiconductor device'20006,067,265'Reference potential generator and a semiconductor memory device having the same'20006,028,782'Data reading method of ferroelectric memory device, and ferroelectric memory device'20005,969,979'Ferroelectric memory device'19995,953,264'Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address'19995,953,277'Reference potential generator and a semiconductor memory device having the same'19995,920,509'Nonvolatile semiconductor memory device capable of conditioning over-erased memory cells'19995,898,608'Method for operating a ferroelectric memory'19995,864,247'Voltage detection circuit, power-on/off reset circuit, and semiconductor device'19995,841,698'Semiconductor device'19985,831,904'Non-volatile semiconductor memory device capable of conditioning over-erased memory cells'19985,828,615'Reference potential generator and a semiconductor memory device having the same'19985,828,619'Semiconductor memory device'19985,760,606'High voltage withstanding circuit and voltage level shifter'19985,751,650'Electric signal supply circuit and semiconductor memory device'19985,751,628'Ferroelectric memory devices and method for testing them'19985,740,114'Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address'19985,706,242'Semiconductor device having a controllable voltage supply'19985,694,445'Semiconductor device with means for charge recycling'19975,687,126'Semiconductor device'19975,675,530'Ferroelectric memory device'19975,650,742'Voltage-level shifter'19975,617,049'Pulse signal generator and redundancy selection signal generator'19975,594,697'Semiconductor device'19975,546,342'Semiconductor memory device including reverse and rewrite means'19965,523,974'Semiconductor memory device with redundant memory cell backup'19965,515,312'Semiconductor memory device'19965,467,302'Semiconductor memory device'19955,430,671'Semiconductor memory device'19955,418,406'Pulse signal generator and redundancy selection signal generator'19955,406,522'Dynamic random access memory device and inspection method thereof'19955,392,234'Semiconductor memory device'19955,375,093'Temperature detecting circuit and dynamic random access memory device'19945,179,298'CMOS buffer circuit which is not influenced by bounce noise'19935,163,168'Pulse signal generator and redundancy selection signal generator'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2008Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (43)· patent assignee history
1992–2014Based in Nara, JP· patent location history
1998–2004Patents assigned to MATSUSHITA ELECTRONICS CORP (13)· patent assignee history
2008–2014Patents assigned to PANASONIC CORP (19)· patent assignee history
2010Based in Kadoma, JP· patent location history
2012–2014Patents assigned to HIRANO HIROSHIGE (11)· patent assignee history
2012–2014Patents assigned to ITOH YUTAKA (6)· patent assignee history
2016–2017Based in Toyama, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MATSUSHITA ELECTRIC INDUSTRIAL CO LTD431992–2008
PANASONIC CORP192008–2014
MATSUSHITA ELECTRONICS CORP131998–2004
HIRANO HIROSHIGEself112012–2014
ITOH YUTAKA62012–2014
Locations
LocationPatentsSpan
Nara, JP761992–2014
Toyama, JP32016–2017
Kadoma, JP12010