LexDanaLexDanabeta
Inventor

Brian A. Winstead

Inventor
Austin, TX, US

Overview

49→
Patents
2007–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 49 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices46%
H01LSemiconductor devices14%
H10BElectronic memory devices14%
B82YSpecific uses or applications of nanostructures9%
G11CStatic stores9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
PatentTitleYear
9,847,389Semiconductor device including an active region and two layers having different stress characteristics20179,449,713'Method for preconditioning thin film storage array for data retention'20169,425,055'Split gate memory cell with a layer of nanocrystals with improved erase performance'20169,379,222'Method of making a split gate non-volatile memory (NVM) cell'20169,343,314'Split gate nanocrystal memory integration'20169,331,160'Split-gate non-volatile memory cells having gap protection zones'20169,257,445'Method of making a split gate non-volatile memory (NVM) cell and a logic transistor'20169,202,930'Memory with discrete storage elements'20159,111,908'Split-gate non-volatile memory cells having improved overlap tolerance'20159,111,867'Split gate nanocrystal memory integration'20158,962,410'Transistors with different threshold voltages'20158,962,416'Split gate non-volatile memory cell'20158,884,358'Method of making a non-volatile memory (NVM) cell structure'20148,885,403'Programming a split gate bit cell'20148,835,295'Split gate memory device with gap spacer'20148,766,362'Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner'20148,724,399'Methods and systems for erase biasing of split-gate non-volatile memory cells'20148,679,912'Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor'20148,643,123'Method of making a semiconductor structure useful in making a split gate non-volatile memory cell'20148,587,039'Method of forming a semiconductor device featuring a gate stressor and semiconductor device'20138,569,858'Semiconductor device including an active region and two layers having different stress characteristics'20138,390,026'Electronic device including a heterojunction region'20138,283,244'Method for forming one transistor DRAM cell structure'20128,263,463'Nonvolatile split gate memory cell having oxide growth'20128,236,638'Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner'20128,163,615'Split-gate non-volatile memory cell having improved overlap tolerance and method therefor'20128,048,738'Method for forming a split gate device'20118,035,156'Split-gate non-volatile memory cell and method'20117,985,649'Method of making a semiconductor structure useful in making a split gate non-volatile memory cell'20117,960,243'Method of forming a semiconductor device featuring a gate stressor and semiconductor device'20117,960,267'Method for making a stressed non-volatile memory device'20117,957,190'Memory having P-type split gate memory cells and method of operation'20117,923,328'Split gate non-volatile memory cell with improved endurance and method therefor'20117,923,769'Split gate non-volatile memory cell with improved endurance and method therefor'20117,833,852'Source/drain stressors formed using in-situ epitaxial growth'20107,821,055'Stressed semiconductor device and method for making'20107,811,886'Split-gate thin film storage NVM cell with reduced load-up/trap-up effects'20107,799,644'Transistor with asymmetry for data storage circuitry'20107,795,091'Method of forming a split gate memory device and apparatus'20107,714,318'Electronic device including a transistor structure having an active region adjacent to a stressor layer'20107,608,898'One transistor DRAM cell structure'20097,572,706'Source/drain stressor and method therefor'20097,488,635'Semiconductor structure with reduced gate doping and methods for forming thereof'20097,479,422'Semiconductor device with stressors and method therefor'20097,468,313'Engineering strain in thick strained-SOI substrates'20087,435,639'Dual surface SOI by lateral epitaxial overgrowth'20087,420,202'Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device'20087,414,877'Electronic device including a static-random-access memory cell and a process of forming the electronic device'20087,166,897'Method and apparatus for performance enhancement in an asymmetrical semiconductor device'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2016Patents assigned to FREESCALE SEMICONDUCTOR INC (47)· patent assignee history
2007–2016Based in Austin, TX, US· patent location history
2010–2017Patents assigned to WINSTEAD BRIAN A (26)· patent assignee history
2012–2016Patents assigned to LOIKO KONSTANTIN V (10)· patent assignee history
2012–2015Patents assigned to KANG SUNG-TAEG (5)· patent assignee history
2012–2015Patents assigned to CHINDALORE GOWRISHANKAR L (3)· patent assignee history
2016–2017Based in Bridgetown, CA· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FREESCALE SEMICONDUCTOR INC472007–2016
WINSTEAD BRIAN Aself262010–2017
LOIKO KONSTANTIN V102012–2016
KANG SUNG-TAEG52012–2015
CHINDALORE GOWRISHANKAR L32012–2015
Locations
LocationPatentsSpan
Austin, Texas, US442007–2016
Bridgetown, CA52016–2017